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Timing Engine isues **ERROR: (TA-152) complaining about generated clock edges (was: an Error during placement?)

icmaple

During placement, it  issue below Error hint , and placement continues.....

**ERROR: (TA-152): A latency path from the 'Fall' edge of the master clock  at source pin 'clk_adc_in' to the 'Fall' edge of generated clock 'clk18' at pin 'u_center_ctrl/u_clk_gen/u_clkmx2x8m_46/Y' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'clk18'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false

Note:  In my sdc file, clk18 defined below:

create_generated_clock -name "clk18"    -edges {1 6 11}  -source [get_ports clk_adc_in]   [get_pins u_center_ctrl/u_clk_gen/clk_tuner_anatv]

Is the clk18 defined incorrectly?

 

Parents

  • I did some learning on this subject and I think I understand better what's going on.  This might make for a subject better tackled in a longer form, but let me take a crack at answering and let me know whether it clarifies the situation.

    The message is indicating that there is an inconsistency between the constraints and what the actual circuit supports.  When looking at issues like this, you need to look at the original create_clock waveform, the edges (or divide_by/multiply_by statements), whether the clock structure is inverted, and whether the flip flop is rising or falling edge triggered.

    If we draw out the the edges for this similar example (which is for a non-inverted circuit, positive edge triggered flip flop) we see a scenario that meets the requirement that all of the edges specified occur on the rising edge of the CLK (ie, the circuit supports the behavior described in the constraints):

     

    In your scenario with edges 1, 6, 11 the problem is that the "6" occurs on a falling edge of the master clock, yet the circuit doesn't support that behavior because the flip flop is triggered on the rising edge.

    The implication of this problem is that although falling edge GEN_CLK paths will be timed, 0 will be used for the source latency value.  You probably don't want this, so you should probably check whether the SDCs describe something the circuit supports.

    You could either make all the edges even numbered (ie, rising to align with rising-edge nature of the flip flop I presume is in your circuit) or assert the recommended "set_global timing_enable_genclk_edge_based_source_latency false" if you want to move past this for a moment and have the timing analysis reflect something that's not possible in the circuit.

    Hope this helps,
    Bob

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  • I did some learning on this subject and I think I understand better what's going on.  This might make for a subject better tackled in a longer form, but let me take a crack at answering and let me know whether it clarifies the situation.

    The message is indicating that there is an inconsistency between the constraints and what the actual circuit supports.  When looking at issues like this, you need to look at the original create_clock waveform, the edges (or divide_by/multiply_by statements), whether the clock structure is inverted, and whether the flip flop is rising or falling edge triggered.

    If we draw out the the edges for this similar example (which is for a non-inverted circuit, positive edge triggered flip flop) we see a scenario that meets the requirement that all of the edges specified occur on the rising edge of the CLK (ie, the circuit supports the behavior described in the constraints):

     

    In your scenario with edges 1, 6, 11 the problem is that the "6" occurs on a falling edge of the master clock, yet the circuit doesn't support that behavior because the flip flop is triggered on the rising edge.

    The implication of this problem is that although falling edge GEN_CLK paths will be timed, 0 will be used for the source latency value.  You probably don't want this, so you should probably check whether the SDCs describe something the circuit supports.

    You could either make all the edges even numbered (ie, rising to align with rising-edge nature of the flip flop I presume is in your circuit) or assert the recommended "set_global timing_enable_genclk_edge_based_source_latency false" if you want to move past this for a moment and have the timing analysis reflect something that's not possible in the circuit.

    Hope this helps,
    Bob

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