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Timing Engine isues **ERROR: (TA-152) complaining about generated clock edges (was: an Error during placement?)

icmaple

During placement, it  issue below Error hint , and placement continues.....

**ERROR: (TA-152): A latency path from the 'Fall' edge of the master clock  at source pin 'clk_adc_in' to the 'Fall' edge of generated clock 'clk18' at pin 'u_center_ctrl/u_clk_gen/u_clkmx2x8m_46/Y' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'clk18'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false

Note:  In my sdc file, clk18 defined below:

create_generated_clock -name "clk18"    -edges {1 6 11}  -source [get_ports clk_adc_in]   [get_pins u_center_ctrl/u_clk_gen/clk_tuner_anatv]

Is the clk18 defined incorrectly?

 

Parents

  • thank you very much,BobD.

    I learnt much from your example.  as for my issue, i found the reason which was a wrong definition of generated clock. it should be -edge { 1 5 11}.   so it is inconsistent with logic topology.  

Reply

  • thank you very much,BobD.

    I learnt much from your example.  as for my issue, i found the reason which was a wrong definition of generated clock. it should be -edge { 1 5 11}.   so it is inconsistent with logic topology.  

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