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Get Boundary Flops list ?

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I am working on hierarchical design.
I want to do a hierarchical bottom up CTS.
At partition level, after CTS, I want to allign the external clocks (The clocks related to input/output delay) with my internal clock to continue the flow.
I need first to characterise my internal postCTS clock network latency.
I need to focus on my boundary flop, I am dealing with useful skew for internal flops...

How can I get this clock latency information only based on boundary flops ?

Is it possible to get the list of boundary flops ?

Any other ideas ?

Pat.


Originally posted in cdnusers.org by bougantp
Parents

  • Dear bougantp:

    1. You can write a FE-TCL script to do this. 1st to get all the ports of your hierarchical block, the trace from this port & get all the registers, this is what you want!
    2. You can report the in2reg & reg2out timing, then use some PERL or VI to achieve this. Seems not easy.

    FYI


    Originally posted in cdnusers.org by eminemshow
Reply

  • Dear bougantp:

    1. You can write a FE-TCL script to do this. 1st to get all the ports of your hierarchical block, the trace from this port & get all the registers, this is what you want!
    2. You can report the in2reg & reg2out timing, then use some PERL or VI to achieve this. Seems not easy.

    FYI


    Originally posted in cdnusers.org by eminemshow
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