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Antenna violation query

amrzahir
I have a question about antenna violations. After I used nanoroute and made post route optimizations (setup, hold, antenna,...etc), it fixed the violations and inserted Antenna cells that my library have. But when making Geometry verification, it reports 10 antenna violations. The problem is that these violations appear to be strange, as all are in power nets !!!!! I have some memory blocks in the design and they are surrounded by M3 & M4 power rings, the violations are in some of these blocks at the intersection between power stripes and these rings. Is there a chance that these violations are due to technology LEF files description of Antenna rules !! And how can I know that Thank you.

  •  Hi,

     There are two different kinds of violations referred to as "antenna" violations.

    There are process antenna violations, which are the kind nanoroute fixes/avoids by layer hopping or diode (antenna cell) insertion, based on the ANTENNA* variables in the LEF file. To check these, run verifyProcessAntenna.These are true process violations that will be completely checked by your signoff DRC run, and need to be fixed.

    There are also "geometry" antenna violations, which are nothing more than a piece of metal extending beyond a ring, stripe, etc. where you probably wanted it to just end at the ring, stripe, etc. These are not technically a real violation as long as they are not breaking any other DRC rules (spacing, width, etc.) and sometimes you can leave them as they are, or you may want to fix them just to have a nice clean design. They are very typically seen in power routing. They are found by verifyGeometry.

    Hope that helps!

    - Kari

  • Hi Kari Thanks a lot, that really helped. The design is clean from process antenna violations. It contains only these geometry violations that you described. Thanks again.

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