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boundary scan chain clock routing

SINGI

 Dear all 

 I could not get any information from various sources so thought abt putting it here, the clock routing for the bounday scan cells is normally implemented through the core digital logic which normally takes awy the routing available for other core.

Now my question, is there a tool or a procedure so  the clock routing of these scan cells are implemented in a different procedure. This way teh clock routing is not through the core digital logic but externally. 

Any one who had worked on this or if they ever had a prob for this. Please share ur experience. I would like to hear all the solutions if any.

 

BR

SING 

Parents

  • Hi SING,

    I've not heard of a technique like this, but I'm a little unclear on how this would work.  When I think of clock routing, it usually involves the addition of buffers and wires and if you're going to do this external to the core digital logic it might help to explain where the buffers would be placed (ie, at the top level in a hierarchical design? outside the core area within a block-based design?).

    If you have information on the building blocks you would need to successfully implement this approach we may be able to help if you describe them in a little more detail.

    Thanks,
    Bob

Reply

  • Hi SING,

    I've not heard of a technique like this, but I'm a little unclear on how this would work.  When I think of clock routing, it usually involves the addition of buffers and wires and if you're going to do this external to the core digital logic it might help to explain where the buffers would be placed (ie, at the top level in a hierarchical design? outside the core area within a block-based design?).

    If you have information on the building blocks you would need to successfully implement this approach we may be able to help if you describe them in a little more detail.

    Thanks,
    Bob

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