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boundary scan chain clock routing

SINGI

 Dear all 

 I could not get any information from various sources so thought abt putting it here, the clock routing for the bounday scan cells is normally implemented through the core digital logic which normally takes awy the routing available for other core.

Now my question, is there a tool or a procedure so  the clock routing of these scan cells are implemented in a different procedure. This way teh clock routing is not through the core digital logic but externally. 

Any one who had worked on this or if they ever had a prob for this. Please share ur experience. I would like to hear all the solutions if any.

 

BR

SING 

Parents

  • Is your scenario where the "clock" buffer is being placed in the middle of the design (floorplan) and fanning out to the respective IO boundary scan cells/modules?   Are you using Cadence RC-DFT to insert boundary scan?  Is it only the clock signal causing you problems?

Reply

  • Is your scenario where the "clock" buffer is being placed in the middle of the design (floorplan) and fanning out to the respective IO boundary scan cells/modules?   Are you using Cadence RC-DFT to insert boundary scan?  Is it only the clock signal causing you problems?

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