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  3. boundary scan chain clock routing

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boundary scan chain clock routing

SINGI
SINGI over 15 years ago

 Dear all 

 I could not get any information from various sources so thought abt putting it here, the clock routing for the bounday scan cells is normally implemented through the core digital logic which normally takes awy the routing available for other core.

Now my question, is there a tool or a procedure so  the clock routing of these scan cells are implemented in a different procedure. This way teh clock routing is not through the core digital logic but externally. 

Any one who had worked on this or if they ever had a prob for this. Please share ur experience. I would like to hear all the solutions if any.

 

BR

SING 

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  • SINGI
    SINGI over 15 years ago

    Hi

    we are using cadence RC-DFT to insert boundary scan and your correct that the clock buffer is being placed in the middle of the design and fanning out to repective IO's. This way we are using a lot of floorplan for buffers in order to meet the timings. But since all the boundary cells get input signals from out side the chip and timing is not critical, 

    Do u have any suggestions or solutions to avoid this ?

     SING

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  • SINGI
    SINGI over 15 years ago

    Hi

    we are using cadence RC-DFT to insert boundary scan and your correct that the clock buffer is being placed in the middle of the design and fanning out to repective IO's. This way we are using a lot of floorplan for buffers in order to meet the timings. But since all the boundary cells get input signals from out side the chip and timing is not critical, 

    Do u have any suggestions or solutions to avoid this ?

     SING

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    • Vote Up 0 Vote Down
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