Is it always necessary to generate a clock tree for a design?

I dont know whether i am asking a crazy question.But I really wonder why designers always use a clock tree, I know the purpose is to reduce skew and latency, but if the gate count is not so big and if the working frequency is around some 50MHz or below, wont it be adequate to use normal routing procedures for clock also ( provided the skew and latency requirements are satisfied) . Or is there any thumb rule that clock should be only routed using CTS only?? In some of the designs i have seen. there are two clocks, one the system clock and other, a clock driving just a single module and my clocks are synchronised already.The second clock driving the single module is a low frequency one and is driving a module having gate count of around 50K. In this scenario can i route the clock like normal net.becuse I think if clock trees can be compromised to some extent, a lot of power can be saved.