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How to handle multiple physical IO pins for a single port?

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When I P&R a huge block, there are situations that I need to place several physical IO pins for a single top level port/net, usually, on different sides of the block for the purpose of easing the higher level connection.   FE looks like only understand one physical IO pin for each port/net and when I did trial route, I found only one physical pin per net(port) was hooked up.  In this way, it coundn't estimate the real routing congestion through the whole block when I have hundreds of such kind cases of multiple IO pins (for each net/port).

How can I let FE know that there are several physical IO pins for a signle port and therefore, it will connect all of them together when it route the block for me?


Originally posted in cdnusers.org by tzhou@micron.com
Parents

  • I don't aware there is any official fix to this issue in FE from Cadence since it may not be reported to Cadence as a bug fix or enhancement request (it is my fault that I only put the issue to this forum and haven't report it to Cadence officially yet). However, If you are only interested in creating a physical route for the extra pins, I have a work-around which you may like to try:

    (1). create a macro (I called it "routeTo") with only one pin "A" and derive the lef file for it and add it into your stdcell LEF file.

    (2). created a eco file to insert this "routeTo" macros to the nets that have extra pins. Your eco file should have lines like:

    ADDINST extra_pin_netName_0 routeTo 1

    INSTTERM A netName

    (3). after "loadECO ecoFile", place those newly added routeTo macro to the location that you like to route to. You can have a placement file that has lines like "placeInstance extra_pin_netName_0 1290.0 2851.0" (don't let the routeTo macros to overlap the extra pins, which may let nanoRoute ignore those routeTo macros)

    Then, nanoRoute should be able to route the nets to the points as you expect.

    Also, somebody told me the "Wroute" engine may be able to take care the physical routing for the extra pins, but I didn't try it out...

    Hope it help! 

    Tongju

     

Reply

  • I don't aware there is any official fix to this issue in FE from Cadence since it may not be reported to Cadence as a bug fix or enhancement request (it is my fault that I only put the issue to this forum and haven't report it to Cadence officially yet). However, If you are only interested in creating a physical route for the extra pins, I have a work-around which you may like to try:

    (1). create a macro (I called it "routeTo") with only one pin "A" and derive the lef file for it and add it into your stdcell LEF file.

    (2). created a eco file to insert this "routeTo" macros to the nets that have extra pins. Your eco file should have lines like:

    ADDINST extra_pin_netName_0 routeTo 1

    INSTTERM A netName

    (3). after "loadECO ecoFile", place those newly added routeTo macro to the location that you like to route to. You can have a placement file that has lines like "placeInstance extra_pin_netName_0 1290.0 2851.0" (don't let the routeTo macros to overlap the extra pins, which may let nanoRoute ignore those routeTo macros)

    Then, nanoRoute should be able to route the nets to the points as you expect.

    Also, somebody told me the "Wroute" engine may be able to take care the physical routing for the extra pins, but I didn't try it out...

    Hope it help! 

    Tongju

     

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