• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Digital Implementation
  3. Encounter crashes

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 92
  • Views 13584
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Encounter crashes

asicman
asicman over 15 years ago

 Hi,

 I'm new to Encounter and I'm trying to get familiar with it. Encounter crashes when I try to use Wroute (global and final routing). Here is the output:

 


begin checkout products ...
Encounter_C 5.2
End checkout products.

Begin LEF/DEF in ...
Reading "project/libs/NangateOpenCellLibrary.lef" ...
Reading ".wroute.19027.def" ...
   *WARNING* design has no clock net
   *WARNING* design has no power net
   *WARNING* design has no ground net
   A total of 3 warnings.
Read in 20 layers, 10 routing layers, 1 overlap layer
Read in 134 macros, 16 used
Read in 61 components
  61 core components: 0 unplaced, 61 placed, 0 fixed
Read in 13 physical pins
  13 physical pins: 0 unplaced, 13 placed, 0 fixed
Read in 67 nets
Read in 213 terminals

Design has preferred via(s).

Distribution of nets (excluding special nets):
       24 ( 2        term),     26 ( 3        term),      7 ( 4        term),
        4 ( 5        term),      3 ( 6        term),      3 ( 7        term),
        0 (>=2000    term).
End LEF/DEF in: cpu: 0:00:01, real: 0:00:01, peak: 14.36 megs.

Begin global routing ...
Begin building data ...
Using automatically generated gcell grid instead of specified gcell grid

Gcell summary:
Layer             Gcell        Blocked Gcell        0-Track Gcell
-----------------------------------------------------------------
 1st routing       4410          0 (  0.00%)          0 (  0.00%)
 2nd routing       4410          0 (  0.00%)          0 (  0.00%)
 3rd routing       4410          0 (  0.00%)          0 (  0.00%)
 4th routing       4410          0 (  0.00%)          0 (  0.00%)
 5th routing       4410          0 (  0.00%)          0 (  0.00%)
 6th routing       4410          0 (  0.00%)          0 (  0.00%)
 7th routing       4410          0 (  0.00%)          0 (  0.00%)
 8th routing       4410          0 (  0.00%)          0 (  0.00%)
 9th routing       4410          0 (  0.00%)          0 (  0.00%)
10th routing       4410          0 (  0.00%)          0 (  0.00%)
-----------------------------------------------------------------
                  44100          0 (  0.00%)          0 (  0.00%)
End building data: cpu: 0:00:02, real: 0:00:02, peak: 78.58 megs.

Begin routing ...
Layer            Length   Down-Via  Over-track     Over-capacity
----------------------------------------------------------------
 1st routing        118          0           0       0 (  0.00%)
 2nd routing        489        247           0       0 (  0.00%)
 3rd routing        187        141           0       0 (  0.00%)
 4th routing         19          1           0       0 (  0.00%)
 5th routing          0          0           0       0 (  0.00%)
 6th routing          0          0           0       0 (  0.00%)
 7th routing          0          0           0       0 (  0.00%)
 8th routing          0          0           0       0 (  0.00%)
 9th routing          0          0           0       0 (  0.00%)
10th routing          0          0           0       0 (  0.00%)
----------------------------------------------------------------
                    813        389           0       0 (  0.00%)

Over-capacity details
Layer              1-2 tracks      3-4 tracks      5-6 tracks      >=7 tracks
------------------------------------------------------------------------------
 1st routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 2nd routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 3rd routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 4th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 5th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 6th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 7th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 8th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 9th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
10th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
------------------------------------------------------------------------------
                    0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
End routing: cpu: 0:00:00, real: 0:00:00, peak: 78.58 megs.

Begin pass 1 optimization ...
Layer            Length   Down-Via  Over-track     Over-capacity
----------------------------------------------------------------
 1st routing        117          0           0       0 (  0.00%)
 2nd routing        498        253           0       0 (  0.00%)
 3rd routing        188        131           0       0 (  0.00%)
 4th routing         18          1           0       0 (  0.00%)
 5th routing          0          0           0       0 (  0.00%)
 6th routing          0          0           0       0 (  0.00%)
 7th routing          0          0           0       0 (  0.00%)
 8th routing          0          0           0       0 (  0.00%)
 9th routing          0          0           0       0 (  0.00%)
10th routing          0          0           0       0 (  0.00%)
----------------------------------------------------------------
                    821        385           0       0 (  0.00%)

Over-capacity details
Layer              1-2 tracks      3-4 tracks      5-6 tracks      >=7 tracks
------------------------------------------------------------------------------
 1st routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 2nd routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 3rd routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 4th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 5th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 6th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 7th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 8th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
 9th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
10th routing        0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
------------------------------------------------------------------------------
                    0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)      0 ( 0.00%)
End pass 1 optimization: cpu: 0:00:00, real: 0:00:00, peak: 78.58 megs.
End global routing: cpu: 0:00:02, real: 0:00:02, peak: 78.58 megs.

Begin final routing ...
Begin building data ...
End building data: cpu: 0:00:00, real: 0:00:00, peak: 78.58 megs.

Begin routing ...
Layer          H-Length   V-Length   Down-Via  Violation
--------------------------------------------------------
 1st routing        439          2          0         15
 2nd routing          7       1136        348          0
 3rd routing        271          0         59          0
 4th routing          0         47          9          0
 5th routing          1          0          2          0
 6th routing          0          0          0          0
 7th routing          0          0          0          0
 8th routing          0          0          0          0
 9th routing          0          0          0          0
10th routing          0          0          0          0
--------------------------------------------------------
                    719       1186        418         15
End routing: cpu: 0:00:16, real: 0:00:16, peak: 78.58 megs.

Begin pass 1 search repair ...
Layer          H-Length   V-Length   Down-Via  Violation
--------------------------------------------------------
 1st routing        439          3          0          1
 2nd routing          7       1135        343          0
 3rd routing        271          0         59          0
 4th routing          0         47          7          0
 5th routing          1          0          2          0
 6th routing          0          0          0          0
 7th routing          0          0          0          0
 8th routing          0          0          0          0
 9th routing          0          0          0          0
10th routing          0          0          0          0
--------------------------------------------------------
                    719       1186        411          1
End pass 1 search repair: cpu: 0:00:00, real: 0:00:01, peak: 78.58 megs.

Begin pass 2 search repair ...
Layer          H-Length   V-Length   Down-Via  Violation
--------------------------------------------------------
 1st routing        439          3          0          1
 2nd routing          7       1135        343          0
 3rd routing        271          0         59          0
 4th routing          0         47          7          0
 5th routing          1          0          2          0
 6th routing          0          0          0          0
 7th routing          0          0          0          0
 8th routing          0          0          0          0
 9th routing          0          0          0          0
10th routing          0          0          0          0
--------------------------------------------------------
                    719       1186        411          1
End pass 2 search repair: cpu: 0:00:00, real: 0:00:00, peak: 78.58 megs.

Begin pass 3 search repair ...
Layer          H-Length   V-Length   Down-Via  Violation
--------------------------------------------------------
 1st routing        439          3          0          0
 2nd routing          7       1135        343          0
 3rd routing        271          0         59          0
 4th routing          0         47          7          0
 5th routing          1          0          2          0
 6th routing          0          0          0          0
 7th routing          0          0          0          0
 8th routing          0          0          0          0
 9th routing          0          0          0          0
10th routing          0          0          0          0
--------------------------------------------------------
                    719       1186        411          0
End pass 3 search repair: cpu: 0:00:00, real: 0:00:00, peak: 78.58 megs.
End final routing: cpu: 0:00:17, real: 0:00:17, peak: 78.58 megs.

Begin DB out ...
Writing "binaryTo7Seg.wdb" ...
Written out 20 layers, 10 routing layers, 1 overlap layer
Written out 134 macros, 16 used
Written out 61 components
  61 core components: 0 unplaced, 61 placed, 0 fixed
Written out 13 physical pins
  13 physical pins: 0 unplaced, 13 placed, 0 fixed
Written out 67 nets, 67 routed
Written out 213 terminals
Written out 44100 gcells for 10 layers
Written out 284 real and virtual terminals
End DB out: cpu: 0:00:00, real: 0:00:00, peak: 78.58 megs.

Begin LEF/DEF/REF out ...
Writing ".wroute.19027.ref" ...
End LEF/DEF/REF out: cpu: 0:00:00, real: 0:00:00, peak: 78.58 megs.

Begin checkin products ...
Encounter_C
End checkin products.

Begin final report ...
Total wire length                    =       1905 (       719x       1186y)
Total number of vias                 =        411
Total number of violations           =          0
Total number of over capacity gcells =          0 (  0.00%)
Total CPU time used                  =    0:00:19
Total real time used                 =    0:00:50
Maximum memory used                  =   78.58 megs
End final report.

*** End WROUTE on Wed Nov 25 16:10:18 2009 ***
Reading REF file ".wroute.19027.ref" ...
version 1.000000
design binaryTo7Seg
status frouted
--- CASESENSITIVE ON
--- DIVIDERCHAR "/"
--- BUSBITCHARS "[]"
--- UnitsPerDBU = 1.0000
there are 70 columns
there are 63 rows
there are 27 vias
Encounter terminated by internal (SEGV) error/signal...
*** Stack trace in log file.

  • Cancel
Parents
  • asicman
    asicman over 15 years ago
    Hi Brad Tree, After doing the routing I realized that the wroute should not have been used. I am learning to use Encounter so I'm going a lot of experimenting with the program. I hope you don't mind if I ask a few questions and would appreciate whatever assistance you can provide: -When is says: *WARNING* design has no clock net *WARNING* design has no power net *WARNING* design has no ground net I guess this is saying that I did not use encounter power planning to properly place my ground and power nets? But would this cause wroute to fail? -I read in some tutorials that we need an io file to specify the io pads, but I have however read some others which design without using the io file. Would this be something that is absolutely needed for the final design? After I used nanoroute (tsmc 018 technology) on my design, I see that it made connections to the boundaries of the chip for the io ports. Does this imply that the io file is not necessary? Thank you. -
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • asicman
    asicman over 15 years ago
    Hi Brad Tree, After doing the routing I realized that the wroute should not have been used. I am learning to use Encounter so I'm going a lot of experimenting with the program. I hope you don't mind if I ask a few questions and would appreciate whatever assistance you can provide: -When is says: *WARNING* design has no clock net *WARNING* design has no power net *WARNING* design has no ground net I guess this is saying that I did not use encounter power planning to properly place my ground and power nets? But would this cause wroute to fail? -I read in some tutorials that we need an io file to specify the io pads, but I have however read some others which design without using the io file. Would this be something that is absolutely needed for the final design? After I used nanoroute (tsmc 018 technology) on my design, I see that it made connections to the boundaries of the chip for the io ports. Does this imply that the io file is not necessary? Thank you. -
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information