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How to control the minimum area of metal and via

Lipengit

I'm using SoC Encounter 7.1 and IBM 0.13um CMOS.

When P&R is finished in Encounter, it said that there is no DRC violation. 

However, when I imported the layout to Virtuoso and used Calibre to run the DRC, there are 80,000 errors about minimum area of M1.

I just wonder how to control the minimum area of M1 in Encounter.

I think LEF file already set up these constrains, but why the violation still happens?

It is impossible for me to fix these 80,000 DRC errors by hand. There must have some solutions in Encounter.

Thanks.

Parents

  •  Hi ,

     I had faced a similar issue in my past experience. I had checked the  both  lef and calibre DRC Rule deck , which seems to be different for a single parameter.

     i.e. for example , in your case minarea constraint might be different lef and DRC rule deck and it might be overconstrained in DRD.

    So as an alternative, i hacked the lef with the overconstrained value present in DRC rule deck and perfomed pnr .

    Hence, the issue is resolved.

    Regards,

    K.VISWANADH BABU

Reply

  •  Hi ,

     I had faced a similar issue in my past experience. I had checked the  both  lef and calibre DRC Rule deck , which seems to be different for a single parameter.

     i.e. for example , in your case minarea constraint might be different lef and DRC rule deck and it might be overconstrained in DRD.

    So as an alternative, i hacked the lef with the overconstrained value present in DRC rule deck and perfomed pnr .

    Hence, the issue is resolved.

    Regards,

    K.VISWANADH BABU

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