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SDC file-HOLD and Setup Time

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Hi,
I am just starting using the nano encounter tool. I just wonder if the sdc file we give to the encounter tool should be the same as SDC file we give to the RTL compiler?
I want to connect my synthesized block to a memory with specific setup hold time. Does anyone has an idea how to give the encounter tool the specific setup time and hold time? how to put a constrain on its output and input port for setup and hold time?

Thanks,

Houman
 


Originally posted in cdnusers.org by houmanh
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  • Hi,

    In my sdc, there are "if { [info exist some_variable_name] } { ... #for RTL ...} else { ... # for gate level ... }

    The different can be due to many reasons, like uncertainty, different in clk pin name (e.g. for RC, in RTL it is called clk, but in gate it can be other names), negative hold check for set_clock_gating_check (RC or primetime might not support negative clock gating check), constraint related to compression logic for ATPG, or mbist (does not exist in RTL), generated clock for RTL (RC does not support generated clock appear in the dotlib, but FE is able to support) etc etc.

    I usually load in another SDC constrain file during P&R (loadTimingCon -incr). What is in this file has to do with the strategy you want to due with timing closure etc. For example, I will tune some clocks during physical synthesis, or force keep some cells, or disable some timing arc (e.g. due to FE does not support rise/fall_{from/to/through} yet. Just be careful that what should not be in the additional SDC when performing sign-off STA.

    For your other question on connect a block to the memory, I think it is related to "set_output_delay -min/max" and "set_input_delay -min/max". Consider adding a virtual clock to the I/O.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
Reply

  • Hi,

    In my sdc, there are "if { [info exist some_variable_name] } { ... #for RTL ...} else { ... # for gate level ... }

    The different can be due to many reasons, like uncertainty, different in clk pin name (e.g. for RC, in RTL it is called clk, but in gate it can be other names), negative hold check for set_clock_gating_check (RC or primetime might not support negative clock gating check), constraint related to compression logic for ATPG, or mbist (does not exist in RTL), generated clock for RTL (RC does not support generated clock appear in the dotlib, but FE is able to support) etc etc.

    I usually load in another SDC constrain file during P&R (loadTimingCon -incr). What is in this file has to do with the strategy you want to due with timing closure etc. For example, I will tune some clocks during physical synthesis, or force keep some cells, or disable some timing arc (e.g. due to FE does not support rise/fall_{from/to/through} yet. Just be careful that what should not be in the additional SDC when performing sign-off STA.

    For your other question on connect a block to the memory, I think it is related to "set_output_delay -min/max" and "set_input_delay -min/max". Consider adding a virtual clock to the I/O.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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