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  3. SDC file-HOLD and Setup Time

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SDC file-HOLD and Setup Time

archive
archive over 18 years ago

Hi,
I am just starting using the nano encounter tool. I just wonder if the sdc file we give to the encounter tool should be the same as SDC file we give to the RTL compiler?
I want to connect my synthesized block to a memory with specific setup hold time. Does anyone has an idea how to give the encounter tool the specific setup time and hold time? how to put a constrain on its output and input port for setup and hold time?

Thanks,

Houman
 


Originally posted in cdnusers.org by houmanh
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  • archive
    archive over 18 years ago

    Hi Bob,
    Interentingly when I introduce the hold time to the tool with a negative value it works fine and it does the hold fix!
    so I guess in set_output_delay -min (hold_time)  , hold time should be added as a negative value!  is this true?
    Thanks so much,

    Houman

    and here is the tcl file I use:
    set design bist_collar
    loadConfig ${design}.conf
    loadIoFile  io.io -noAdjustDieSize
    setCteReport
    setMaxRouteLayer 4
    set dbgLefDefOutVersion 5.5
    timeDesign -prePlace
    loadFPlan ${design}.fp
    source power.tcl
    setPlaceMode -timingdriven -reorderScan -mediumEffort -noCongOpt
    placeDesign -inPlaceOpt -prePlaceOpt
    optDesign -preCts    
    setCTSMode -topPreferredLayer 3 -bottomPreferredLayer 2 -routeClkNet \
     -useCTSRouteGuide -postOpt
    clockDesign
    loadTimingCon -incr design.sdc
    set step postCts
    saveDesign $step.enc
    optDesign -postCts -hold
    getNanoRouteMode -quiet
    getNanoRouteMode -quiet envSuperThreading
    setNanoRouteMode -quiet -drouteFixAntenna true
    setNanoRouteMode -quiet -routeInsertAntennaDiode true
    setNanoRouteMode -quiet -routeAntennaCellName ANTENNA
    setNanoRouteMode -quiet -timingEngine CTE
    setNanoRouteMode -quiet -routeWithTimingDriven true
    setNanoRouteMode -quiet -routeWithEco false
    setNanoRouteMode -quiet -routeWithSiDriven true
    setNanoRouteMode -quiet -routeTdrEffort 0
    setNanoRouteMode -quiet -routeSiEffort high
    setNanoRouteMode -quiet -routeWithSiPostRouteFix false
    setNanoRouteMode -quiet -drouteAutoStop true
    setNanoRouteMode -quiet -routeSelectedNetOnly false
    setNanoRouteMode -quiet -drouteStartIteration default
    setNanoRouteMode -quiet -envNumberProcessor 1
    setNanoRouteMode -quiet -drouteEndIteration default
    generateTracks
    globalDetailRoute
    optDesign -postRoute -setup -hold
    optDesign -postRoute
    setFillerMode -corePrefix FILL -core "FILL64 FILL32 FILL16 FILL8 FILL4 FILL2 FILL1"
    addFiller
    addMetalFill
    set step postRoute
    saveDesign $step.enc -def
    verifyGeometry
    verifyConnectivity -type regular -error 1000 -warning 50
    verifyConnectivity -type special -noAntenna -noUnConnPin -error 1000 -warning 50
    verifyProcessAntenna
    extractRC
    rcOut -spef $step.enc.dat/$design.spef.gz
    delayCal -sdf $step.enc.dat/$design.sdf



    # Final timing report after metal fill
    timeDesign -postRoute -hold
    timeDesign -postRoute

    exit


    Originally posted in cdnusers.org by houmanh
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  • archive
    archive over 18 years ago

    Hi Bob,
    Interentingly when I introduce the hold time to the tool with a negative value it works fine and it does the hold fix!
    so I guess in set_output_delay -min (hold_time)  , hold time should be added as a negative value!  is this true?
    Thanks so much,

    Houman

    and here is the tcl file I use:
    set design bist_collar
    loadConfig ${design}.conf
    loadIoFile  io.io -noAdjustDieSize
    setCteReport
    setMaxRouteLayer 4
    set dbgLefDefOutVersion 5.5
    timeDesign -prePlace
    loadFPlan ${design}.fp
    source power.tcl
    setPlaceMode -timingdriven -reorderScan -mediumEffort -noCongOpt
    placeDesign -inPlaceOpt -prePlaceOpt
    optDesign -preCts    
    setCTSMode -topPreferredLayer 3 -bottomPreferredLayer 2 -routeClkNet \
     -useCTSRouteGuide -postOpt
    clockDesign
    loadTimingCon -incr design.sdc
    set step postCts
    saveDesign $step.enc
    optDesign -postCts -hold
    getNanoRouteMode -quiet
    getNanoRouteMode -quiet envSuperThreading
    setNanoRouteMode -quiet -drouteFixAntenna true
    setNanoRouteMode -quiet -routeInsertAntennaDiode true
    setNanoRouteMode -quiet -routeAntennaCellName ANTENNA
    setNanoRouteMode -quiet -timingEngine CTE
    setNanoRouteMode -quiet -routeWithTimingDriven true
    setNanoRouteMode -quiet -routeWithEco false
    setNanoRouteMode -quiet -routeWithSiDriven true
    setNanoRouteMode -quiet -routeTdrEffort 0
    setNanoRouteMode -quiet -routeSiEffort high
    setNanoRouteMode -quiet -routeWithSiPostRouteFix false
    setNanoRouteMode -quiet -drouteAutoStop true
    setNanoRouteMode -quiet -routeSelectedNetOnly false
    setNanoRouteMode -quiet -drouteStartIteration default
    setNanoRouteMode -quiet -envNumberProcessor 1
    setNanoRouteMode -quiet -drouteEndIteration default
    generateTracks
    globalDetailRoute
    optDesign -postRoute -setup -hold
    optDesign -postRoute
    setFillerMode -corePrefix FILL -core "FILL64 FILL32 FILL16 FILL8 FILL4 FILL2 FILL1"
    addFiller
    addMetalFill
    set step postRoute
    saveDesign $step.enc -def
    verifyGeometry
    verifyConnectivity -type regular -error 1000 -warning 50
    verifyConnectivity -type special -noAntenna -noUnConnPin -error 1000 -warning 50
    verifyProcessAntenna
    extractRC
    rcOut -spef $step.enc.dat/$design.spef.gz
    delayCal -sdf $step.enc.dat/$design.sdf



    # Final timing report after metal fill
    timeDesign -postRoute -hold
    timeDesign -postRoute

    exit


    Originally posted in cdnusers.org by houmanh
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