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SDC file-HOLD and Setup Time

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Hi,
I am just starting using the nano encounter tool. I just wonder if the sdc file we give to the encounter tool should be the same as SDC file we give to the RTL compiler?
I want to connect my synthesized block to a memory with specific setup hold time. Does anyone has an idea how to give the encounter tool the specific setup time and hold time? how to put a constrain on its output and input port for setup and hold time?

Thanks,

Houman
 


Originally posted in cdnusers.org by houmanh
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  • archive

    Hi,

    Thanks for your reply. Here is some more information of the results I got when using different polarity for hold time:
    first SDC:  (the clock period is 4ns)
    set_output_delay -clock [get_clocks {clk}]  -min 1  [get_ports {mem_d}]
    set_output_delay -clock [get_clocks {clk}]  -max .3 [get_ports {mem_d}]
    so here I try to satisfy the memory setup and hold time which is going to be attached to the output port of the synthesized block.
    and here is the results I get:
    +--------------------+---------+
    |     Hold mode      |   all   |
    +--------------------+---------+
    |           WNS (ns):|  0.137  |
    |           TNS (ns):|  0.000  |
    |    Violating Paths:|    0    |
    |          All Paths:|   128   |
    +--------------------+---------+

    +--------------------+---------+---------+---------+---------+---------+---------+
    |     Hold mode      |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
    +--------------------+---------+---------+---------+---------+---------+---------+
    |           WNS (ns):|  0.139  |  0.139  |  3.006  |  0.365  |  3.955  |   N/A   |
    |           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |  0.000  |   N/A   |
    |    Violating Paths:|    0    |    0    |    0    |    0    |    0    |   N/A   |
    |          All Paths:|   128   |   106   |   104   |   21    |   18    |   N/A   |
    +--------------------+---------+---------+---------+---------+---------+---------+

    secodn SDC: (only difference hold time with negative value)
    set_output_delay -clock [get_clocks {clk}]  -min -1  [get_ports {mem_d}]
    set_output_delay -clock [get_clocks {clk}]  -max .3 [get_ports {mem_d}]
    results;

    +--------------------+---------+
    |     Hold mode      |   all   |
    +--------------------+---------+
    |           WNS (ns):| -0.833  |
    |           TNS (ns):| -12.468 |
    |    Violating Paths:|   18    |
    |          All Paths:|   128   |
    +--------------------+---------+
    *** Started fixing hold violations (CPU=0:00:00.2, totcpu=0:00:14.1, mem=220.5M)
    *info: PostCts hold fixing, Slew prop level: 0
    Density before buffering = 0.498 (fixHold)
    *info:
    *Info: The following delay and buffer cells will be used for hold fixing
    *Info:    cell  igArea   setupDelay f/r(inTran f/r, load)    holdDelay (inTran f/r, load)
    *Info:                     nanoSecond  ( nanoSecond  PF )    nanoSecond (nanoSecond  PF )
    *Info:   BUFFD0    4.0   0.055/0.057 (0.071/0.071, 0.009)   0.122/0.135 (0.131/0.131, 0.009)
    *Info:   CKBXD0    4.0   0.059/0.056 (0.071/0.071, 0.009)   0.13................and etc
    and here is the hold time after doing fix hold
    +--------------------+---------+---------+---------+---------+---------+---------+
    |     Hold mode      |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
    +--------------------+---------+---------+---------+---------+---------+---------+
    |           WNS (ns):|  0.007  |  0.138  |  3.003  |  0.007  |  1.957  |   N/A   |
    |           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |  0.000  |   N/A   |
    |    Violating Paths:|    0    |    0    |    0    |    0    |    0    |   N/A   |
    |          All Paths:|   128   |   106   |   104   |   21    |   18    |   N/A   |
    +--------------------+---------+---------+---------+---------+---------+---------+


    so I guess as I want my output changes after some delay from the positive edge of the clock , i have to introduce the hold time with negative value. I appreciate your comment on this.

    Thanks,

    Houman




    Originally posted in cdnusers.org by houmanh
Reply
  • archive

    Hi,

    Thanks for your reply. Here is some more information of the results I got when using different polarity for hold time:
    first SDC:  (the clock period is 4ns)
    set_output_delay -clock [get_clocks {clk}]  -min 1  [get_ports {mem_d}]
    set_output_delay -clock [get_clocks {clk}]  -max .3 [get_ports {mem_d}]
    so here I try to satisfy the memory setup and hold time which is going to be attached to the output port of the synthesized block.
    and here is the results I get:
    +--------------------+---------+
    |     Hold mode      |   all   |
    +--------------------+---------+
    |           WNS (ns):|  0.137  |
    |           TNS (ns):|  0.000  |
    |    Violating Paths:|    0    |
    |          All Paths:|   128   |
    +--------------------+---------+

    +--------------------+---------+---------+---------+---------+---------+---------+
    |     Hold mode      |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
    +--------------------+---------+---------+---------+---------+---------+---------+
    |           WNS (ns):|  0.139  |  0.139  |  3.006  |  0.365  |  3.955  |   N/A   |
    |           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |  0.000  |   N/A   |
    |    Violating Paths:|    0    |    0    |    0    |    0    |    0    |   N/A   |
    |          All Paths:|   128   |   106   |   104   |   21    |   18    |   N/A   |
    +--------------------+---------+---------+---------+---------+---------+---------+

    secodn SDC: (only difference hold time with negative value)
    set_output_delay -clock [get_clocks {clk}]  -min -1  [get_ports {mem_d}]
    set_output_delay -clock [get_clocks {clk}]  -max .3 [get_ports {mem_d}]
    results;

    +--------------------+---------+
    |     Hold mode      |   all   |
    +--------------------+---------+
    |           WNS (ns):| -0.833  |
    |           TNS (ns):| -12.468 |
    |    Violating Paths:|   18    |
    |          All Paths:|   128   |
    +--------------------+---------+
    *** Started fixing hold violations (CPU=0:00:00.2, totcpu=0:00:14.1, mem=220.5M)
    *info: PostCts hold fixing, Slew prop level: 0
    Density before buffering = 0.498 (fixHold)
    *info:
    *Info: The following delay and buffer cells will be used for hold fixing
    *Info:    cell  igArea   setupDelay f/r(inTran f/r, load)    holdDelay (inTran f/r, load)
    *Info:                     nanoSecond  ( nanoSecond  PF )    nanoSecond (nanoSecond  PF )
    *Info:   BUFFD0    4.0   0.055/0.057 (0.071/0.071, 0.009)   0.122/0.135 (0.131/0.131, 0.009)
    *Info:   CKBXD0    4.0   0.059/0.056 (0.071/0.071, 0.009)   0.13................and etc
    and here is the hold time after doing fix hold
    +--------------------+---------+---------+---------+---------+---------+---------+
    |     Hold mode      |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
    +--------------------+---------+---------+---------+---------+---------+---------+
    |           WNS (ns):|  0.007  |  0.138  |  3.003  |  0.007  |  1.957  |   N/A   |
    |           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |  0.000  |   N/A   |
    |    Violating Paths:|    0    |    0    |    0    |    0    |    0    |   N/A   |
    |          All Paths:|   128   |   106   |   104   |   21    |   18    |   N/A   |
    +--------------------+---------+---------+---------+---------+---------+---------+


    so I guess as I want my output changes after some delay from the positive edge of the clock , i have to introduce the hold time with negative value. I appreciate your comment on this.

    Thanks,

    Houman




    Originally posted in cdnusers.org by houmanh
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