SDC file-HOLD and Setup Time

Hi,

Thanks for your reply. Here is some more information of the results I got when using different polarity for hold time:
first SDC:  (the clock period is 4ns)
set_output_delay -clock [get_clocks {clk}]  -min 1  [get_ports {mem_d}]
set_output_delay -clock [get_clocks {clk}]  -max .3 [get_ports {mem_d}]
so here I try to satisfy the memory setup and hold time which is going to be attached to the output port of the synthesized block.
and here is the results I get:
+--------------------+---------+
|     Hold mode      |   all   |
+--------------------+---------+
|           WNS (ns):|  0.137  |
|           TNS (ns):|  0.000  |
|    Violating Paths:|    0    |
|          All Paths:|   128   |
+--------------------+---------+

+--------------------+---------+---------+---------+---------+---------+---------+
|     Hold mode      |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
|           WNS (ns):|  0.139  |  0.139  |  3.006  |  0.365  |  3.955  |   N/A   |
|           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |  0.000  |   N/A   |
|    Violating Paths:|    0    |    0    |    0    |    0    |    0    |   N/A   |
|          All Paths:|   128   |   106   |   104   |   21    |   18    |   N/A   |
+--------------------+---------+---------+---------+---------+---------+---------+

secodn SDC: (only difference hold time with negative value)
set_output_delay -clock [get_clocks {clk}]  -min -1  [get_ports {mem_d}]
set_output_delay -clock [get_clocks {clk}]  -max .3 [get_ports {mem_d}]
results;

+--------------------+---------+
|     Hold mode      |   all   |
+--------------------+---------+
|           WNS (ns):| -0.833  |
|           TNS (ns):| -12.468 |
|    Violating Paths:|   18    |
|          All Paths:|   128   |
+--------------------+---------+
*** Started fixing hold violations (CPU=0:00:00.2, totcpu=0:00:14.1, mem=220.5M)
*info: PostCts hold fixing, Slew prop level: 0
Density before buffering = 0.498 (fixHold)
*info:
*Info: The following delay and buffer cells will be used for hold fixing
*Info:    cell  igArea   setupDelay f/r(inTran f/r, load)    holdDelay (inTran f/r, load)
*Info:                     nanoSecond  ( nanoSecond  PF )    nanoSecond (nanoSecond  PF )
*Info:   BUFFD0    4.0   0.055/0.057 (0.071/0.071, 0.009)   0.122/0.135 (0.131/0.131, 0.009)
*Info:   CKBXD0    4.0   0.059/0.056 (0.071/0.071, 0.009)   0.13................and etc
and here is the hold time after doing fix hold
+--------------------+---------+---------+---------+---------+---------+---------+
|     Hold mode      |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
|           WNS (ns):|  0.007  |  0.138  |  3.003  |  0.007  |  1.957  |   N/A   |
|           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |  0.000  |   N/A   |
|    Violating Paths:|    0    |    0    |    0    |    0    |    0    |   N/A   |
|          All Paths:|   128   |   106   |   104   |   21    |   18    |   N/A   |
+--------------------+---------+---------+---------+---------+---------+---------+


so I guess as I want my output changes after some delay from the positive edge of the clock , i have to introduce the hold time with negative value. I appreciate your comment on this.

Thanks,

Houman

here is the figure explaining what I try to achieve as a memory hold time,

sorry if it is too obvious and trivial!

Hi Houmanh,

I believe the use of -1ns for set_output_delay is okay. Actually you should look at the timing report (and not the timing summary) to check the details of the timing calculation. set_output_delay is the amount of delay on the data path that is outside the chip. By setting a -1ns, the signal inside the chip that pass through mem_d will seem to be faster by 1ns, and this is bad.

But you should still study the detail timing report (the one that show both launching clock, receiving clock and data path). As you associate mem_d to an internal clock, it will has a clock latency due to clock tree too. This is true if you somehow output the clock and also balance it. Also, consider the option "-add_delay" for set_output_delay. Lastly, you might want to consider using virtual clock for I/O;I feel that it is more flexible.

Regards,
Eng Han

Thanks Eng Han.