Stats

  • Locked Locked
  • Replies 1
  • Subscribers 91
  • Views 13009
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

PKS retiming

comport

Hi

 I am trying to use the do_pipeline_check / do_pipeline_retime features in PKS, on a block with 4 layers of pipeline built-in. Since the combinatorial function is not easy to pipeline manually (not an arithmetic function but a decoder), I put it between 2 pipeline stages hoping for PKS to remap it through all the available stages by using do_pipeline_check / do_pipeline_retime.

The check works but tells me that no register is retimable.

Anybody knows what are the criteria for a register to be re-timable ?

Thanks

Parents

  • Hi comport,

    I have not used PKS in a while so its criteria may vary slightly. The general criteria for retiming is based on classes. For example a flop on CLKA will be on one class and one on CLKB will be on a different class so no retiming across different classes. The case of different clocks is quite an obvious one since moving flops across clock domains carries pretty evident dangers. Other class criterias are things like asynchronous signals feeding the flops, enable signals for stalling flops, etc. Regarding stalling flops an enable signals, not that the inference of clock gating can also have an impact on the ability of tools to apply retiming techniques. Last but not least I wonder why you are not using RTL Compiler instead of PKS. Synthesis technology is a substantial upgrade, not to mention support for CPF and linkage for Conformal and other tools. In the future, synthesis related questions are probably better suited for the Logic Design forum.

    hope this helps,

    gh-

Reply

  • Hi comport,

    I have not used PKS in a while so its criteria may vary slightly. The general criteria for retiming is based on classes. For example a flop on CLKA will be on one class and one on CLKB will be on a different class so no retiming across different classes. The case of different clocks is quite an obvious one since moving flops across clock domains carries pretty evident dangers. Other class criterias are things like asynchronous signals feeding the flops, enable signals for stalling flops, etc. Regarding stalling flops an enable signals, not that the inference of clock gating can also have an impact on the ability of tools to apply retiming techniques. Last but not least I wonder why you are not using RTL Compiler instead of PKS. Synthesis technology is a substantial upgrade, not to mention support for CPF and linkage for Conformal and other tools. In the future, synthesis related questions are probably better suited for the Logic Design forum.

    hope this helps,

    gh-

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.