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Delete all buffers between IO ang register

spach

hi

i need to delete all series of buffers with fanput 1 from input to register & register to output

one way is using deletebuffertree command with selected nets(nets b/w buffers).

can any one tell me how i can get all net names between input & register, register & output using encounter db commands.

regards,

suresh pachha  

Parents

  • I think using a CTS-like approach to build buffer trees for datapaths should only be used when you require balanced latency.  I doubt you need that, so I wouldn't pursue the ckSynthesis nor bufferTreeSynthesis.

    What is the design challenge you're trying to overcome?  Is it poor in2reg timing?  If so, I'd try to get the tool to place the registers closer to IO pins in the first place.  A couple of techniques you could try for this:

    1. Specify the flops as jtag instances and run the jtag placement prior to placeDesign.
    2. There's a utility in the gifts directory (<install_path>/share/fe/gift/scripts/tcl/userAddMenuPullInstsToIos.tcl) that traces and preplaces instances "n" levels from the IO pin close to the IO pin. 

    If the concern is something other than in2reg timing, let us know and we can suggest a different approach.  optDesign should be doing a fine job buffering these paths- could you describe a little more about what it's doing poorly?

    It's possible that in2reg timing is mis-constrained.  It's pretty common to see IO constraints that are unachievable due to including source latency or not -or- there being difficulty generating timing budgets in general.

    Hope this helps,
    Bob

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  • I think using a CTS-like approach to build buffer trees for datapaths should only be used when you require balanced latency.  I doubt you need that, so I wouldn't pursue the ckSynthesis nor bufferTreeSynthesis.

    What is the design challenge you're trying to overcome?  Is it poor in2reg timing?  If so, I'd try to get the tool to place the registers closer to IO pins in the first place.  A couple of techniques you could try for this:

    1. Specify the flops as jtag instances and run the jtag placement prior to placeDesign.
    2. There's a utility in the gifts directory (<install_path>/share/fe/gift/scripts/tcl/userAddMenuPullInstsToIos.tcl) that traces and preplaces instances "n" levels from the IO pin close to the IO pin. 

    If the concern is something other than in2reg timing, let us know and we can suggest a different approach.  optDesign should be doing a fine job buffering these paths- could you describe a little more about what it's doing poorly?

    It's possible that in2reg timing is mis-constrained.  It's pretty common to see IO constraints that are unachievable due to including source latency or not -or- there being difficulty generating timing budgets in general.

    Hope this helps,
    Bob

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