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How to make SoC Encounter export Verilog with VDD/VSS pins

LogicWizard

Hi, folks,

After Design Compiler, the gate-level Verilog does not have any VDD/VSS pins for each cell, e.g.

INVD1 U1 (.A(n1), .Z(n2))

Then this Verilog is imported to SoC Encounter. After P&R, is there anyway to make SoC Encounter export final Verilog with added VDD/VSS pins for each cell?

INVD1 U1(.A(n1), .Z(n2), .VDD(VDD), .VSS(VSS))

For LEF file VDD/VSS are listed for each cell, but while .lib does not have them.

Please help.

Thanks

 

  • BobD

    Hi LogicWizard,

    It sounds like "saveNetlist -phys" is what you're looking for.  Could you have a look and let us know whether that does the job?

    Thanks,
    Bob

  • atwork

    I have another question relating to this issue.

    In the database, the power names are defined as vdd! and gnd!. Is this OK?

    When saveNetlist -phys is done, it save the netlist .\vdd (\vdd!) .

    Is it because of the !  mark?

    Thanks

     

  • wally1

    Yes, if the net name contains a special character such as "!" it must be escaped. As long as it escaped it should be okay. 

    In your example, you have "\.vdd (\vdd!)". It should be ".vdd(\vdd! )". Can you double check this? The pin name should not be escape since it is simply "vdd" and the escaped string needs to have an empty space at the end of it, i.e. "\vdd! "

    Thanks,

    Brian

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