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Adding tie low cells on only requried pins

Hi All,

Iam involved in mixed signal IC design, in which my verilog netlist consists of 1'b0 for some of the pins in digital logic . But, at the same time for some analog custuom blocks, some signal pins has to be connected to the vss. My problem is , the encounter is placing tie low cells on all the pins which is not required for me. So is there any way to eleminate this problem ?

Regards,

K.VISWANADH BABU

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