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max fan out in clock net

SINGI

Dear all 

 

The following are the 2 wrost fanout pins in my design, its clear they clock pin. I tried to optdesign post cts. but they are not fixed. I changes the clock status from fixed but still doest work. Can any one sugges me some sol. 

 

 

# InstPin                   MaxFanLoad  FanLoad         FanLoadSlk       CellPort             Remark   
#
XXXXXX/CN 10.000      67.000          -57.000          CKND8/CN             C        
YYYYYCN 10.000      67.000          -57.000          CKND8/CN             C        
 

  • optDesign will not fix DRV violations on clock nets. You should fix these during Clock Tree Synthesis (CTS). In the CTS constraints file you can use "MaxFanout" to specify the constraint. Note, typically max fanout constraints are soft constraints and DRV fixing during optDesign and CTS focuses more on max tran and cap violations. 

  • wally1 said:

    optDesign will not fix DRV violations on clock nets. You should fix these during Clock Tree Synthesis (CTS). In the CTS constraints file you can use "MaxFanout" to specify the constraint. Note, typically max fanout constraints are soft constraints and DRV fixing during optDesign and CTS focuses more on max tran and cap violations. 

     

     

    So presuming  MaxFanout has been specified - how is that enforced, as it is a soft constraint

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