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clock buffers can't be used during CTS

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Hi!
right now, I am working on a project using SoCE4.2. The library I am using contains these kinds of clock buffers, which are all output complementary, Q and -Q. Unfortunately, while I specified them in my *.ctstch file and ran the CTS, the errors appeared:

ckSynthesis Option :  -rguide digital_cts/digital_cts.guide -report digital_cts/digital_cts.ctsrpt
**WARN: cell CK01D1 has more than one timing arc. Check the timing libraries.
**ERROR:
Buffer CK01D1 specified in the clock tree specification file is invalid.
Usage: ckSynthesis [-clk ] [-report ]
                   [-rguide ] [-macromodel
                   ] [-check] [-forceReconvergent]
                   [-dontFixAddedBuffers] [-breakLoop
                   | -ignoreLoopDetect] [-addOriginalNet]
**ERROR: ERROR: Incorrect usage for command "ckSynthesis".

So I have to use those simple normal buffers & inverter instead. Although this time the CTS succeed, I am not quite satisfied with the CTS result report, cause the discrepancy between the rising skew and falling skew is huge:

Rise Skew                      : 506.3(ps)             
Fall Skew                      : 1358.5(ps) 

I guess this is due to the performance of the simple buffer & inverter is not as good as the clock buffer.So I wanna try to use the clock buffer back in the CTS. Can anybody tell me how to fix this cell-CK01D1-has-more-than-one-timing arc problem?

Thanks in Advance!


Originally posted in cdnusers.org by Gordonlyn
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  • archive

    Thanks for your helps, Kari and bsg. I tried the method you've recommended - to use the inverters only in my

    CTS, and it works! After several times of trial-and-error, I got my results finally:

    Rise Skew : 331.4(ps)
    Fall Skew : 420(ps)
    Max. Rise Buffer Tran : 464.6(ps)
    Max. Fall Buffer Tran : 470.7(ps)
    Max. Rise Sink Tran : 442.6(ps)
    Max. Fall Sink Tran : 468.9(ps)
    Min. Rise Buffer Tran : 6(ps)
    Min. Fall Buffer Tran : 6(ps)
    Min. Rise Sink Tran : 120.1(ps)
    Min. Fall Sink Tran : 104.9(ps)

    Pretty symmetrical comparing with my previous one. :)

    While I was working on the clock buffer problem, writing the set_disable_timing scripts to disable the -Q
    timing arc in my *.sdc file, I still ended up with the same error. I just totally have no idea what to do.
    I think it might be better to make the clock buffer(Q) and inverter work together.


    Originally posted in cdnusers.org by Gordonlyn
Reply
  • archive

    Thanks for your helps, Kari and bsg. I tried the method you've recommended - to use the inverters only in my

    CTS, and it works! After several times of trial-and-error, I got my results finally:

    Rise Skew : 331.4(ps)
    Fall Skew : 420(ps)
    Max. Rise Buffer Tran : 464.6(ps)
    Max. Fall Buffer Tran : 470.7(ps)
    Max. Rise Sink Tran : 442.6(ps)
    Max. Fall Sink Tran : 468.9(ps)
    Min. Rise Buffer Tran : 6(ps)
    Min. Fall Buffer Tran : 6(ps)
    Min. Rise Sink Tran : 120.1(ps)
    Min. Fall Sink Tran : 104.9(ps)

    Pretty symmetrical comparing with my previous one. :)

    While I was working on the clock buffer problem, writing the set_disable_timing scripts to disable the -Q
    timing arc in my *.sdc file, I still ended up with the same error. I just totally have no idea what to do.
    I think it might be better to make the clock buffer(Q) and inverter work together.


    Originally posted in cdnusers.org by Gordonlyn
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