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  3. clock buffers can't be used during CTS

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clock buffers can't be used during CTS

archive
archive over 18 years ago

Hi!
right now, I am working on a project using SoCE4.2. The library I am using contains these kinds of clock buffers, which are all output complementary, Q and -Q. Unfortunately, while I specified them in my *.ctstch file and ran the CTS, the errors appeared:

ckSynthesis Option :  -rguide digital_cts/digital_cts.guide -report digital_cts/digital_cts.ctsrpt
**WARN: cell CK01D1 has more than one timing arc. Check the timing libraries.
**ERROR:
Buffer CK01D1 specified in the clock tree specification file is invalid.
Usage: ckSynthesis [-clk ] [-report ]
                   [-rguide ] [-macromodel
                   ] [-check] [-forceReconvergent]
                   [-dontFixAddedBuffers] [-breakLoop
                   | -ignoreLoopDetect] [-addOriginalNet]
**ERROR: ERROR: Incorrect usage for command "ckSynthesis".

So I have to use those simple normal buffers & inverter instead. Although this time the CTS succeed, I am not quite satisfied with the CTS result report, cause the discrepancy between the rising skew and falling skew is huge:

Rise Skew                      : 506.3(ps)             
Fall Skew                      : 1358.5(ps) 

I guess this is due to the performance of the simple buffer & inverter is not as good as the clock buffer.So I wanna try to use the clock buffer back in the CTS. Can anybody tell me how to fix this cell-CK01D1-has-more-than-one-timing arc problem?

Thanks in Advance!


Originally posted in cdnusers.org by Gordonlyn
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  • archive
    archive over 17 years ago

    Hi all,

    Please can anybody tell me about how to calculate number of straps,power ring widths for a particular chip( if possible give some examples).

    And also give me the info about how to reduce the power dissipation while doing power planning in the physical design.

    I am waiting for the solution........


    Originally posted in cdnusers.org by mahecadence
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  • archive
    archive over 17 years ago

    Hi all,

    Please can anybody tell me about how to calculate number of straps,power ring widths for a particular chip( if possible give some examples).

    And also give me the info about how to reduce the power dissipation while doing power planning in the physical design.

    I am waiting for the solution........


    Originally posted in cdnusers.org by mahecadence
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