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How can I manually map a library cell to an instance?

drjay
Hi,

I want to insert buffers at the input of a design.
So I created instances in the VHDL-code which have the name mybuf and an "o = i" statement inside.
When importing them into RTL compiler, I can see them as instances.

I thought, I can do the following now to tell the rc that it shall map all of these instances to the library-cell BUFFD24 :

set_attribute libcell /libraries/tcbn90lphpudtc/libcells/BUFFD24 /designs/cab_digi/instances_hier/mybuf*

I get the error:

Warning : Cannot resize an unmapped (i.e. hierarchical or generic) instance. [TUI-268]
: Instance '/designs/cab_digi/instances_hier/buf[4].buf' is not a mapped instance.
Warning : The attribute is not applicable to the object. [TUI-67]

I tried many things but it seems that i am just completely starting at the wrong end...
Would I have to use assignments instead?
like: set_remove_assign_options -buffer_or_inverter BUFFD24

How can I tell rc not to optimize the instances away but to map them to a specific cell?

Any help would be appreciated.
Cheers,
Joachim

  • Hello everybody,
    change_link -instances /designs/cab_digi/instances_hier/buf* -libcell /libraries/tcbn90lphpudtc/libcells/BUFFD24
    did the trick. After synthesis, the cells are still in place.

    However, it seems that not everything is plain vanilla:
    Warning : An instance does not have a dedicated subdesign. [CHLNK-301]
    : Uniquifying subdesign for /designs/cab_digi/instances_hier/buf[0].buf. New subdesign is mybuff_72
    : Change link will uniquify the subdesign.

    Any suggestions whether this is critical or not are wlcome.
    Cheers, Joachim

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