how do i set wire width and space for a particular net?

If you're looking to set routing rules that NanoRoute will follow when doing detailed routing, have a look at:

Route->NanoRoute->Set Attribute

You can set additional spacing on any signal net, but if you want to route (for example) double-width wires you'd need to have or create a non-default rule in your technology LEF and then associate it with the nets you want routed double-width.

Let me know if this isn't what you're looking for.

Thanks,
Bob

Hi Bob,

Using non-default rule for creating wider wires for some specific case,  is well understood. Kari has also explained in a tutorial how to create those rules in a LEF file .

But it is still obscure to me what we should do if we want to have "via arrays" on these wires. By default, it seems we get the default (single) via at each layer chnage.  How can we get the maximum possibe array of vias (like the special vias of the power/ground nets) ?

Could you tell a bit more ?

Thanks

Patrice

I think if the wire gets very wide you'd need to define via array generation rules by hand. If it's just multi-cut vias you're interested in you might try "generateLef -2cutVia" after defining the lef with the wider wires.

-Bob

 Hi Patrice,

You should be able to use the USEVIARULE statement in your NONDEFAULT rule to grab the via rule that you want to use, although if this isn't specified, it should be grabbing your default rules automatically. You can also try the MINCUTS statment in your nondefault rule; please check the LEF manual for details. Let us know if you get it working.

- Kari

Hi All,

     I'm currently having the same problem too.  I set Non-Default Rule to route wider width but it still insert single VIA for these Wider Width. I'm new to Encounter but I recall  IC Compiler is smart enough to do that when I specify the Custom Non-Default Rule with Double Widht/Double Cut ...Some like very strange......I hope Cadence AE can shed some lights on this.

I did try  the %generateLef  -2CutVia    but getting an Error message and obviously it did not work.

** ERROR: (ENCRM-125): There are LEF files loaded. Skip generateLef utility. Please dont load any LEF files before invoking this utility.

Hi Ttran,

First of all, I want to report that I was not able to get it to work, despite trying all the suggestions by Kari.

But I would like to suggest another solution that  was in fact much more powerful for my case. I have used the mixed signal routing capability of Encounter. You can easily control many constraints.  I did that during the floorplan stage. Here is a pratical example to have this running easily:

Encounter command:

#special nets to probe pads
routeMixedSignal -nets {pad_VPPD1 pad_VPPD2} -constraintFile MyConstraint.const

MyConstraint.const  file (in the working directory):

NETS
  WIDTH 8.000000
  SPACING 0.230000
  MAXRES 11.000000
  TAPERING
  MINCUT 16
  ROUTELAYERS M1:M3
     pad_VPPD1
END NETS

NETS
  WIDTH 15.000000
  SPACING 0.230000
  MAXRES 20.000000
  TAPERING
  MINCUT 64
  ROUTELAYERS M1:M3
     pad_VPPD2
END NETS

Please, try it, you will like it !

Patrice

TTran,

Have a look at the generateVias command.

- Kari 

Hello Kari,

I am hoping you can help me with my particular issue.  I am trying to route multiple nets from traditional IO pads to some flip chip pads with the largest possible wire width going from one metal layer up to the top metal layer. The min width is less than a micron and I need to route them with 32 microns or at least as large as I can to avoid ESD issues. There is one metal in-between the two I am routing to, so two sets of vias will at least need to be used when it transitions.  Also, should I do this before standard cell placement or wait to do it with nano routing or before routing everything else?

Hello Kari,

I am hoping you can help me with my particular issue.  I am trying to route multiple nets from traditional IO pads to some flip chip pads with the largest possible wire width going from one metal layer up to the top metal layer. The min width is less than a micron and I need to route them with 32 microns or at least as large as I can to avoid ESD issues. There is one metal in-between the two I am routing to, so two sets of vias will at least need to be used when it transitions.  Also, should I do this before standard cell placement or wait to do it with nano routing or before routing everything else?