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how to avoid this problem?

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   I found some paths easy violation as shown in attechment after CTS. The ICG cell is traced through and the skew is balanced between A and C. But the violation easy occur between A and B(ICG cell). How do I avoid this problem?


Originally posted in cdnusers.org by Dota
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  • A good practice for such ICG cell is to avoid logic from the flop A (Register out).
    Anyway, an alternative to ameliorate timing is to play with ckClone which should push the IGC cell more deeper in the clock tree.

    In pre-CTS mode, if you do have specific trick on your SDC, the TA estimate register A, B and C to be balance.
    By construction we know that register B will be in advance compare to A and C.
    To modelize that, you can add in your SDC
    [i]set_clock_gating_check 1.0 [get_pins {B/E}][/i]
    It will modelize the fact that the clock tree between B and C will take 1.0 ns.
    It will force the pre-CTS optimisation to work more on that path, and to be more in line with your post-CTS db.

    Pat.


    Originally posted in cdnusers.org by bougantp
Reply

  • A good practice for such ICG cell is to avoid logic from the flop A (Register out).
    Anyway, an alternative to ameliorate timing is to play with ckClone which should push the IGC cell more deeper in the clock tree.

    In pre-CTS mode, if you do have specific trick on your SDC, the TA estimate register A, B and C to be balance.
    By construction we know that register B will be in advance compare to A and C.
    To modelize that, you can add in your SDC
    [i]set_clock_gating_check 1.0 [get_pins {B/E}][/i]
    It will modelize the fact that the clock tree between B and C will take 1.0 ns.
    It will force the pre-CTS optimisation to work more on that path, and to be more in line with your post-CTS db.

    Pat.


    Originally posted in cdnusers.org by bougantp
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