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how to avoid this problem?

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   I found some paths easy violation as shown in attechment after CTS. The ICG cell is traced through and the skew is balanced between A and C. But the violation easy occur between A and B(ICG cell). How do I avoid this problem?


Originally posted in cdnusers.org by Dota
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  • thanks for your answer, but there are some problem in it.
    set_clock_gating_check is used for path timing check. The tool don't care about timing check in CTS ,so this command seems useless. I think some methods below maybe helpful.
    1. let the CTS not to balance A and C to reduce clock skew between them.
    2. set max delay between A and B to help tool optimize placement.
    any suggestion is welcome.


    Originally posted in cdnusers.org by Dota
Reply

  • thanks for your answer, but there are some problem in it.
    set_clock_gating_check is used for path timing check. The tool don't care about timing check in CTS ,so this command seems useless. I think some methods below maybe helpful.
    1. let the CTS not to balance A and C to reduce clock skew between them.
    2. set max delay between A and B to help tool optimize placement.
    any suggestion is welcome.


    Originally posted in cdnusers.org by Dota
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