Stats

  • Locked Locked
  • Replies 1
  • Subscribers 92
  • Views 13360
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

RTL compiler synthesis

superman321
I have Verilog STRUCTURAL netlist that Im trying to synthesize in RTL compiler. It is pure combinational Circuit consisting only of regular gates. Though the design has some 8,9 input NAND/NOR and AND/OR gates that im trying to break it to ONLY 2-ip gates. I have library (.lib) only of 2ips gates and when i synthesize the design, although it maps it to 2-ips gates from the library it adds FEED-BACK!. The feedbacks are from primary output of the circuit that fanouts to may gate inputs of the design. Im trying to figure out why the tool when it breaks these big gates adds feedback? or Im missing some commands in my (*.cmd) file? The aim is only to break the big gates (ip >2) to map it to 2ip gates. Any help will be greatly appreciated.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.