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HOLD FIX FLOW IN ENCOUNTER

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Can anyone please explain the hold fix flow to be followed in encounter. I am trying to put a dontuse on many buffer cells but they are still being used when I use the FIXHOLD and optDesign -hold command.
Also it would help if yusers could commnent  on how good is encounter in fixing Hold. What are the techniwues used by encounter to fix hold. Does it use only delay insetion in the datapath or does much more to optimize hold violations


Originally posted in cdnusers.org by mvvijay78
Parents

  • I have not had too much luck with hold fixing. It adds a lot of buffers and our designs are quite tight as far as utilization is concerned. So I have had congestion problems created by hold fixing.

    After CTS I usually go through clock reports in detail to see why skews didn't get fixed properly. Usually the culprits are one of the following -
    a) Floorplan needs to be revisited. Too many routes, density issues.
    b) Is shielding turned on? In smaller technologies I have seen that 2x spacing is better than shielding. Also allocate enough layers for clock routing.
    c) Remove the larger buffers from the CTS buffer list
    d) Adding the inverting CT cells to the buffer list sometimes helps with skew issues.
    e) Do you have generated clocks - If this is the case, make sure that the "through pins" are coming out correctly in your clock spec file. Make sure that the root pin and the source pin are defined correctly in the SDC. If this doesnt work try doing a 2 step CTS - you can find an article on this in the cadence website.
    f) See if there are reconvergent paths in your clock tree. Use -forceReconvergent option in CTS.


    Thx,

    Sanjay


    Originally posted in cdnusers.org by ssunder@sioptical.com
Reply

  • I have not had too much luck with hold fixing. It adds a lot of buffers and our designs are quite tight as far as utilization is concerned. So I have had congestion problems created by hold fixing.

    After CTS I usually go through clock reports in detail to see why skews didn't get fixed properly. Usually the culprits are one of the following -
    a) Floorplan needs to be revisited. Too many routes, density issues.
    b) Is shielding turned on? In smaller technologies I have seen that 2x spacing is better than shielding. Also allocate enough layers for clock routing.
    c) Remove the larger buffers from the CTS buffer list
    d) Adding the inverting CT cells to the buffer list sometimes helps with skew issues.
    e) Do you have generated clocks - If this is the case, make sure that the "through pins" are coming out correctly in your clock spec file. Make sure that the root pin and the source pin are defined correctly in the SDC. If this doesnt work try doing a 2 step CTS - you can find an article on this in the cadence website.
    f) See if there are reconvergent paths in your clock tree. Use -forceReconvergent option in CTS.


    Thx,

    Sanjay


    Originally posted in cdnusers.org by ssunder@sioptical.com
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