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Power routing issues

Hello,

I am using SOC 6.2 and 90nm technology. I followed partitioned flow and after updating and flattening the top-level design, I started power planning. After setting up power rings and stripes, when I verified geometry and connectivity, I got following voilations at many instances. As I am new to encounter environment so don't know how to rectify those.

1. Verify Geometry: (I got this violation at all of my I/O Pin instances)

IOPin

Actual: 0.019 Min: 0.07

False: No Layer: m2

2. Verify Connitivity (After setting up power rings, stripes and running sRoute)

NoRoute Violations (1000)

Net Clk

False: No

Net P[0]

False: No

This list goes on and on....

Any help regarding how to solve these issues shall highly be appriciated.

Affaq

mikhail over 15 years ago

Hello,
Am I right that DRCs are between power rings/stripes/pins and signal wires?
Mikhail
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affaq over 15 years ago

Yes Mikhail thats true. I have modified my custom cells and now I have a prBoundary with a spacing of .605um along top and bottom of the cells but still I get these violation.
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