"generate statements" in RTLCompilation

 Hi Kamal,

you must have a typo being that you used generate statements exhaustively. The code provided is not compliant with LRM hence it will likely not compile in RTL Compiler or most other self-respecting synthesis tools.Can you clarify what your module declaration is trying to do? It does not even have a proper port declaration (BTW, port declarations are ilegal in generate blocks)

Following is a simple example you can try that illustrates what I think you are trying to do. Just read with read_hdl -v2001 or read_hdl -sv, elab, and synthesize and should produce expected results

module top (
              input wire clk, in,
       output wire out
              );
   parameter xyz = 1'b1;

   generate
       if (xyz == 1'b1) begin
          dummy d1 (.in(in), .clk(clk), .out(out) );
       end
       else begin
          assign out = in && clk;
       end
   endgenerate

endmodule // top

module dummy (
                input wire clk, in,
         output reg out
         );

always @(posedge clk) begin
       out <= in;
end

endmodule
               
drop an email if you still have questions

regards,

gh-