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Control signal distribution network

Shawn

situation : CMOS05 subchip with 128 memories in a 4X32 array approximately 1X4 mm
Timing closure problems are related to the common control signals going to 128 memories wrappers.
The signals are correctly sourced near the center of the subchip , but the insane serpentine path
that the initial trialroute takes puts the the farthest memories on the end of a 16 mm long wire.
To top it off opt Design -preCts starts off following this insane initial trialRoute and the later
tries in vain to fix it during optCritPath.


Ideally a wire spline up the center with separate taps for each row pair.
I do not care if it is balanced, I am just trying to minimize the worst insertion delay.

What is the best automated way to distribute these common control signals?
I have a manual method that involves routing blockages and routing selected nets ,
but this is time consuming and error prone.

Shawn

  •  You could try bufferTreeSynthesis. This builds a tree for non-clock nets. You also have the right idea with routing these nets first (via the routeSelecteNet setting). Let us know how bufferTreeSynthesis works, if you try it.

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