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LEC - gated clock latches "Unreachable"

Hello,

LEC between RTL and gate level after gated clock insertion reports all the gated clock latches as "Unreachable".

Is there some constrain or command in LEC which should be implemented to resolve this issue?

Thank you very much!

Boris

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croy over 15 years ago

Hi Boris

This is expected behaviour. During modeling Conformal takes the latch circuit and changes it back to a mux so equivalence checking can be run. Please see Solution 11195852 for more details.

Chrystian
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croy over 15 years ago

Hi Boris

This is expected behaviour. During modeling Conformal takes the latch circuit and changes it back to a mux so equivalence checking can be run. Please see Solution 11195852 for more details.

Chrystian
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