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Can CTS stop tracing on hierarchical module ports?

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Dear community,

my clock signal is connected to the clock network on the one hand. On the other hand it is connected to a module's input. Within this module the signal is always used as a data signal (chip is switched to different mode of operation for this).

This module contains logic, therefore CTS traces through the input ports. AFAIK tracing can only stop at top level ports or leaf cell pins.

Is there any way to make CTS stop tracing at the module's input port (like ExcludedPin/ExcludedPort - which don't work)?

Many thanks in advance for your suggestions!


Originally posted in cdnusers.org by agruebl
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  • archive

    Hi agruebl,

    You need the "LeafPin" command in your ".ctstch" file on the input pin of the first device(s) in your module.

    If you look at the "Encounter User Guide" (soceUG.pdf), "Synthesizing Clock Trees" (Chapter 11),
    Product Version 6.2.2 (SOC6.2), August 2007, on Page 477, you will see the following:

    LeafPin
    + pinName rising | falling
    + …


    Marks the input pin as a “leaf” pin for non-clock-type
    instances, stops tracing, and balances clock skew.
    Note: Use the LeafPin statement only with input pins.
    CTS ignores LeafPin statements that are associated
    with output pins.

    Choose one of the following:
    rising - CTS treats the input pin as a risingedge-
    triggered flip-flop clock pin.
    falling - CTS treats the input pin as a fallingedge-
    triggered flip-flop clock pin.

    Here's a real life example. These are input pins of devices where clock was stopped
    from tracing through combinational logic gates.

    LeafPin
    + i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/a1
    + i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/a2
    + i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/b1
    + i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/b2


    Regards - R.M.


    Originally posted in cdnusers.org by raul63
Reply
  • archive

    Hi agruebl,

    You need the "LeafPin" command in your ".ctstch" file on the input pin of the first device(s) in your module.

    If you look at the "Encounter User Guide" (soceUG.pdf), "Synthesizing Clock Trees" (Chapter 11),
    Product Version 6.2.2 (SOC6.2), August 2007, on Page 477, you will see the following:

    LeafPin
    + pinName rising | falling
    + …


    Marks the input pin as a “leaf” pin for non-clock-type
    instances, stops tracing, and balances clock skew.
    Note: Use the LeafPin statement only with input pins.
    CTS ignores LeafPin statements that are associated
    with output pins.

    Choose one of the following:
    rising - CTS treats the input pin as a risingedge-
    triggered flip-flop clock pin.
    falling - CTS treats the input pin as a fallingedge-
    triggered flip-flop clock pin.

    Here's a real life example. These are input pins of devices where clock was stopped
    from tracing through combinational logic gates.

    LeafPin
    + i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/a1
    + i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/a2
    + i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/b1
    + i_macro/i_core/i_usb_device_top/i_usb_asyn_hand/asyn_hand_ps1/u19/b2


    Regards - R.M.


    Originally posted in cdnusers.org by raul63
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