Stats

  • Locked Locked
  • Replies 20
  • Subscribers 90
  • Views 19612
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Can CTS stop tracing on hierarchical module ports?

archive

Dear community,

my clock signal is connected to the clock network on the one hand. On the other hand it is connected to a module's input. Within this module the signal is always used as a data signal (chip is switched to different mode of operation for this).

This module contains logic, therefore CTS traces through the input ports. AFAIK tracing can only stop at top level ports or leaf cell pins.

Is there any way to make CTS stop tracing at the module's input port (like ExcludedPin/ExcludedPort - which don't work)?

Many thanks in advance for your suggestions!


Originally posted in cdnusers.org by agruebl
Parents

  • Hi raul63,

    many thanks for your answer! Unfortunately it doesn't fix my problem... What I did not mention is that I switch (not regularly but I do ;-) ) between cell libraries and the input pins have different names in the diff. libraries.

    So I wanted to have a somewhat technology independent solution and define the module's input port as a leaf. Consequently CTS would have to either:
    * automatically treat all directly connected cell inputs (inside the module) as leaf pins, or
    * treat the module input as a leaf.

    The second point is probably impossible because CTS wouldn't "know" where to stop tracing when using this module port without physical pins. So the question is wether the firts point is feasible.

    One (rather time consuming) solution I am currently thinking about is to extract the names of the leaf pins connected to the module port using a TCL script and to insert these names into the ".ctsh" file using a PERL script or something.

    Hope this describes my problem a bit more precisely... any ideas? ;-)

    Regards,
    Andreas


    Originally posted in cdnusers.org by agruebl
Reply

  • Hi raul63,

    many thanks for your answer! Unfortunately it doesn't fix my problem... What I did not mention is that I switch (not regularly but I do ;-) ) between cell libraries and the input pins have different names in the diff. libraries.

    So I wanted to have a somewhat technology independent solution and define the module's input port as a leaf. Consequently CTS would have to either:
    * automatically treat all directly connected cell inputs (inside the module) as leaf pins, or
    * treat the module input as a leaf.

    The second point is probably impossible because CTS wouldn't "know" where to stop tracing when using this module port without physical pins. So the question is wether the firts point is feasible.

    One (rather time consuming) solution I am currently thinking about is to extract the names of the leaf pins connected to the module port using a TCL script and to insert these names into the ".ctsh" file using a PERL script or something.

    Hope this describes my problem a bit more precisely... any ideas? ;-)

    Regards,
    Andreas


    Originally posted in cdnusers.org by agruebl
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.