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Can CTS stop tracing on hierarchical module ports?

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Dear community,

my clock signal is connected to the clock network on the one hand. On the other hand it is connected to a module's input. Within this module the signal is always used as a data signal (chip is switched to different mode of operation for this).

This module contains logic, therefore CTS traces through the input ports. AFAIK tracing can only stop at top level ports or leaf cell pins.

Is there any way to make CTS stop tracing at the module's input port (like ExcludedPin/ExcludedPort - which don't work)?

Many thanks in advance for your suggestions!


Originally posted in cdnusers.org by agruebl
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    Hi Andreas,

    I have never tried what you are attempting to do, however,
    in the Encounter User's Guide, there is the following command,
    which I am assuming would declare a module port as a "LeafPort":

    LeafPort
    + portName rising | falling
    + …

    Marks the port as a “leaf” port for non-clock-type
    instances, stops tracing, and balances clock skew.
    Choose one of the following:
    rising CTS treats the pin as a rising-edgetriggered
    flip-flop clock pin.
    falling CTS treats the pin as a falling-edgetriggered
    flip-flop clock pin.


    From Encounter User Guide
    Synthesizing Clock Trees
    August 2007 Product Version 6.2.2, p. 478

    Regards - R.M.


    Originally posted in cdnusers.org by raul63
Reply
  • archive

    Hi Andreas,

    I have never tried what you are attempting to do, however,
    in the Encounter User's Guide, there is the following command,
    which I am assuming would declare a module port as a "LeafPort":

    LeafPort
    + portName rising | falling
    + …

    Marks the port as a “leaf” port for non-clock-type
    instances, stops tracing, and balances clock skew.
    Choose one of the following:
    rising CTS treats the pin as a rising-edgetriggered
    flip-flop clock pin.
    falling CTS treats the pin as a falling-edgetriggered
    flip-flop clock pin.


    From Encounter User Guide
    Synthesizing Clock Trees
    August 2007 Product Version 6.2.2, p. 478

    Regards - R.M.


    Originally posted in cdnusers.org by raul63
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