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  3. Can CTS stop tracing on hierarchical module ports?

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Can CTS stop tracing on hierarchical module ports?

archive
archive over 17 years ago

Dear community,

my clock signal is connected to the clock network on the one hand. On the other hand it is connected to a module's input. Within this module the signal is always used as a data signal (chip is switched to different mode of operation for this).

This module contains logic, therefore CTS traces through the input ports. AFAIK tracing can only stop at top level ports or leaf cell pins.

Is there any way to make CTS stop tracing at the module's input port (like ExcludedPin/ExcludedPort - which don't work)?

Many thanks in advance for your suggestions!


Originally posted in cdnusers.org by agruebl
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  • archive
    archive over 17 years ago

    @raul63:
    I have tried this but CTS gives the warning

    **WARN: The LeafPort + sn_top/rx_delay/rx_del0_0_/in is an invalid name.

    for every hierarchical port that I specify (product version 5.2.6). This option seems a bit useless, provided it accepts only top level ports as arguments?

    @bsg:
    ... I'm trying to avoid GUI usage in our design flow (after floorplanning) ;-) Unfortunately some instance names do change after intermediate re-synthesis runs.

    @eminemshow:
    This seems to exactly solve my problem. But my software doesn't recognize the db commands. Are these OpenAccess commands (not available here)? I couldn't even find them in the SKILL manual..
    Anyway, I will try to do this all in TCL using get_pins and all_connected etc. Thanks for the hint!


    Thank you all for you help! Great forum! :-)


    Originally posted in cdnusers.org by agruebl
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  • archive
    archive over 17 years ago

    @raul63:
    I have tried this but CTS gives the warning

    **WARN: The LeafPort + sn_top/rx_delay/rx_del0_0_/in is an invalid name.

    for every hierarchical port that I specify (product version 5.2.6). This option seems a bit useless, provided it accepts only top level ports as arguments?

    @bsg:
    ... I'm trying to avoid GUI usage in our design flow (after floorplanning) ;-) Unfortunately some instance names do change after intermediate re-synthesis runs.

    @eminemshow:
    This seems to exactly solve my problem. But my software doesn't recognize the db commands. Are these OpenAccess commands (not available here)? I couldn't even find them in the SKILL manual..
    Anyway, I will try to do this all in TCL using get_pins and all_connected etc. Thanks for the hint!


    Thank you all for you help! Great forum! :-)


    Originally posted in cdnusers.org by agruebl
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