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Design simulation (Lib generation) with Encounter Library characterizer

OLyonnais

 Good morning,

When i lauch my script for ELC i get 57 tests passed and 2 failed. Reading the .log, i don't arrive to find the mistake.

here the display message:

 with the ELC tool:

   DESIGN        PROCESS       #ID         STATUS     IPDB
-------------+-------------+----------+--------------+-----------

MUX31   typical       D0000          PASSED    MUX31

MUX31   typical       D0001          PASSED    MUX31

[....]

MUX31   typical       D0026          FAILED    MUX31
MUX31   typical       D0027          FAILED    MUX31

[....]

MUX31   typical       D0043          PASSED    MUX31
MUX31   typical       D0044          PASSED    MUX31
MUX31   typical       D0045          PASSED    MUX31
MUX31   typical       D0046          PASSED    MUX31
MUX31   typical       D0047          PASSED    MUX31
MUX31   typical       D0048          PASSED    MUX31
MUX31  typical       R0000          PASSED    MUX31
MUX31  typical       R0001          PASSED    MUX31
MUX31  typical       R0002          PASSED    MUX31
MUX31  typical       R0003          PASSED    MUX31
MUX31  typical       R0004          PASSED    MUX31
MUX31   typical       R0005          PASSED    MUX31
MUX31   typical       R0006          PASSED   MUX31
MUX31  typical       R0007          PASSED    MUX31
MUX31   typical       R0008          PASSED    MUX31
MUX31  typical       R0009          PASSED    MUX31
============|=============|=============|==========|==============
MUX31   typical       59         57            MUX31
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
               Simulation Summary               
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
-------------+-------------+----------+--------------+-----------
-------------+-------------+----------+------------+-----------+------------
   DESIGN    |   PROCESS   |   #ID    |   STAGE    |  STATUS   |    IPDB
-------------+-------------+----------+------------+-----------+------------
MUX31   typical       D0026     VERIFICATE   FAIL        MUX31
MUX31  typical       D0027     VERIFICATE   FAIL        MUX31
-------------+-------------+----------+------------+----------

 

******************************************************

When i have a look on the .log corresponding to D0027 and D0026 for example i have this warning

 D0026.log

Total 25 waveforms translated to DB
D0    :    L -> L
D1    :    L -> L
D2    :    L -> L
S0    :    H -> H
S0N    :    L -> L
S1    :    R -> R
S1N    :    F -> F
Z    :    R -> L
[WARNING(dssimchk)] Z : simulated value mismatch with estimated value.
VDD    :    H -> H
GND    :    L -> L
NET080    :    H -> H
Verification aborted
Releasing lock
 

 D0027.log

Total 25 waveforms translated to DB
D0    :    L -> L
D1    :    H -> H
D2    :    L -> L
S0    :    H -> H
S0N    :    L -> L
S1    :    R -> R
S1N    :    F -> F
Z    :    F -> H
[WARNING(dssimchk)] Z : simulated value mismatch with estimated value.
VDD    :    H -> H
GND    :    L -> L
NET080    :    L -> L
Verification aborted
Releasing lock
 

 ***********************************************************

and a example of a passed one:  D0023.log

Total 25 waveforms translated to DB
D0    :    H -> H
D1    :    L -> L
D2    :    L -> L
S0    :    F -> F
S0N    :    R -> R
S1    :    L -> L
S1N    :    H -> H
Z    :    R -> R
VDD    :    H -> H
GND    :    L -> L
NET080    :    L -> L
Waveform matching done

Waveform measurment done

Releasing lock


----------------------------------------------

Thank you for your aids 

  • Dear OLyonnais,

    Please check the Spice log file which is saved *.work/ directory whether there is spice failure. The *.work directory will be kept when you use the option "db_spice -keep_work". 

    Regards,
    Keeshik Oh

  • I'm somewhat of a novice looking for information troubleshooting cad-elc errors.  I have a DFF that passes DRC, LVS and for all intents and purposes does what I think it should.  However, when I try to characterize the cell in cad-elc it passes up to 75%, but fails all the remaining tests.

    I suspect it is because its running tests on my CLK and _CLK inputs and"over-characterizes the cell" and doesn't understand it's testing cases that will never occur.

    Any indicators where I can look would be greatly apprciated or even some tutorials I can cut my teeth on.

    excerpts from cad-elc

     -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
                   Simulation Summary                
    -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
    -------------+-------------+----------+--------------+-----------
    -------------+-------------+----------+------------+-----------+------------
       DESIGN    |   PROCESS   |   #ID    |   STAGE    |  STATUS   |    IPDB
    -------------+-------------+----------+------------+-----------+------------
    DFFLAB3        typical       D0000     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0001     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0002     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0003     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0004     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0005     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0006     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0007     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0008     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0009     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0010     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0011     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0012     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0013     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0014     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0015     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0016     VERIFICATE   PASS        foo         
    DFFLAB3        typical       D0017     VERIFICATE   PASS        foo         
    DFFLAB3        typical       R0000     SIMULATE     FAIL        foo         
    DFFLAB3        typical       R0001     SIMULATE     FAIL        foo         
    DFFLAB3        typical       R0002     SIMULATE     FAIL        foo         
    DFFLAB3        typical       R0003     SIMULATE     FAIL        foo         
    DFFLAB3        typical       R0004     SIMULATE     FAIL        foo         
    DFFLAB3        typical       R0005     SIMULATE     FAIL        foo         
    -------------+-------------+----------+------------+----------

    [INFO(db_spice)] Check the encounterlc.log/<ipdb_name>/<DESIGN>_<PROCESS>_<ID>.log file to determine the cause of the failure. The SPICE simulation log file can be found in the /home/xxxxxxxx/IC_CAD/5710/ELC/encounterlc.work/<DESIGN>_<PROCESS>_<ID>/ directory.

    -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
     - Total Simulation : 24
     - Total Passed     : 18(75.00%)
     - Total Failed     : 6(25.00%)

    ....................................................................................................................................................................................................................

     

    Running on Machine lab2-18
        SIMULATOR : spectre
        file : /home/xxxxxxxx/IC_CAD/5710/ELC/encounterlc.work/foo.work/DFFLAB3_typical_R0000/typical_R0000_tr.sp (for binary search) is created.
    Search Simulation deck created in /home/xxxxxxxx/IC_CAD/5710/ELC/encounterlc.work/foo.work/DFFLAB3_typical_R0000
    * *  ************************************  * *
    * *  BINARY SEARCH for Timing Constraints  * *
    * *  ************************************  * *
    Using command spectre
    Simulation failed with the status 256
    [ERROR(dssearch)] simulation aborted
    Command dssearch aborted
    Releasing lock

    Keeshik said:

    Dear OLyonnais,

    Please check the Spice log file which is saved *.work/ directory whether there is spice failure. The *.work directory will be kept when you use the option "db_spice -keep_work". 

    Regards,
    Keeshik Oh

    ...................................................................................................................................................................................................................

     

  • Could you try the latest ELC verion first? If you still get the same error, pelase provide the test case.

    Keeshik

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