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Open ports in special route summary

Greatrebel

Hi All,

I got a summary after special routing below. It shows there are some ports open for stripe and core. But when I use verifyConnectivity to check, there are no violations. Is that a serious issue for PnR. How can I locate these open ports. Thanks in advanced

  Number of IO ports routed: 4
  Number of Block ports routed: 6
  Number of Stripe ports routed: 80  open: 2
  Number of Core ports routed: 185  open: 399
  Number of Power Bump ports routed: 0
  Number of Followpin connections: 292
  4 ports open due to poor power planning

Parents

  •  Hi Kari,

    I run the verifyAClimit again after nanoroute, the result is below

     encounter 9> verifyACLimit

    ******** Start: verifyACLimit ********
    Start Time: Thu Jun 17 21:24:10 2010

    Irms Scale Factor: 1
    Report File: top.aclimit.rpt
    Timing Analysis Mode: CTE
    Verifying all signal nets.

    Num Violations: 0

    The reportclocktree command can know the frequency from clock spec file. I am wondering whether verifyACLimit can know the frequency of my design, since the default frequency is 500 in ACCURRENTDENSITY RMS table. But my design has one clock at 50MHz and the other is 25MHz. I use verifyACLimitSetFreq before verifyACLimit, but the result is same. I did not use any special setting for routing clock during nanoroute and how can I know how many buffers/inverters have been inserted in clock tree?

    Thank you very much again

     

Reply

  •  Hi Kari,

    I run the verifyAClimit again after nanoroute, the result is below

     encounter 9> verifyACLimit

    ******** Start: verifyACLimit ********
    Start Time: Thu Jun 17 21:24:10 2010

    Irms Scale Factor: 1
    Report File: top.aclimit.rpt
    Timing Analysis Mode: CTE
    Verifying all signal nets.

    Num Violations: 0

    The reportclocktree command can know the frequency from clock spec file. I am wondering whether verifyACLimit can know the frequency of my design, since the default frequency is 500 in ACCURRENTDENSITY RMS table. But my design has one clock at 50MHz and the other is 25MHz. I use verifyACLimitSetFreq before verifyACLimit, but the result is same. I did not use any special setting for routing clock during nanoroute and how can I know how many buffers/inverters have been inserted in clock tree?

    Thank you very much again

     

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