Stats

  • Locked Locked
  • Replies 5
  • Subscribers 91
  • Views 16186
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

how to remove constant value flops?

tompy

 Hi :

 I got an IP from vendor. Due to design change, some part of the IP are not needed. Since it is time consuming to ask the vendor to remove those flops, I wish to do it in synthesis. I tied the unused part IP clock port and reset_n port to 0. And I want RTL compiler remove those unclocked/always reset flops.I have try set_attribute optimize_constant_0_seq true unclocke_register

but it doesn't work. Can anyone help me? thx!!

 

/tompy

Parents
  • tompy

    Hi grasshopper:

    Thx for your reply. The IP has multi AHB master ports, we remove 1 master so one of the AHB master ports related signals are all tied to 0 (ex: AHB7_HCLK, AHB7_HRESETN....) 

    I think there maybe some input ports related to those registers are not tied at 0.

    But what I am curious is that I am sure the clock port(AHB7_HCLK) is tied to 0 and reset_n (AHB7_HRESETN) port is tied to 0. 

    My question is that I think make CLK and resetn tied to 0 is good enough to guarantee those registers are staying in their reset state, which is constant.

    Will RC treat them as constant flops and remove them since they are always reset? Or I need to ensure all the logic related to the flop's Data port is static (that's kind of a huge work)?

Reply
  • tompy

    Hi grasshopper:

    Thx for your reply. The IP has multi AHB master ports, we remove 1 master so one of the AHB master ports related signals are all tied to 0 (ex: AHB7_HCLK, AHB7_HRESETN....) 

    I think there maybe some input ports related to those registers are not tied at 0.

    But what I am curious is that I am sure the clock port(AHB7_HCLK) is tied to 0 and reset_n (AHB7_HRESETN) port is tied to 0. 

    My question is that I think make CLK and resetn tied to 0 is good enough to guarantee those registers are staying in their reset state, which is constant.

    Will RC treat them as constant flops and remove them since they are always reset? Or I need to ensure all the logic related to the flop's Data port is static (that's kind of a huge work)?

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.