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  3. Missing net and Cell Names-exporting gds2 from encounter...

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Missing net and Cell Names-exporting gds2 from encounter , importing it in Caliber

asinghct
asinghct over 15 years ago
Hi, I am missing net as well as cell name information when I am exporting GDS2 from encounter and importing it into caliber (for RC+ coupling capacitance) extraction. Any suggestions on how to do it. Thanks Amit
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  • Kari
    Kari over 15 years ago

     I'm not familiar with this way of running Calibre, but when you say "library file", do you mean the spice subckt files? Make sure the spice of your std cells is included.

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  • asinghct
    asinghct over 15 years ago
    I tried using v2lvs Kept the options as v2lvs -o ouput.sp -s spice_lib.sp -v cirk.v When I see the benchmark output.sp has power and ground ports missing for every module. Therefore the lvs fails.. Do u think the issue is with my power/gnd routing by any case thanks
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  • Kari
    Kari over 15 years ago

     For LVS, you need to use a physical verilog. In Encounter:

     saveNetlist -phys myDesign.v

    See if that gets you past this issue.

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  • asinghct
    asinghct over 15 years ago

    Hi, 

    Unfortunately its not. working. Pls find enclosed the encounter config, encounter scripts. I am using  encounter first time, since I am in student my setup is very basic for academic research purpose (goal was to extract RC+Coup)  in dspf

    thanks

     

    ################################################
    #                                              #
    #  FirstEncounter Input configuration file     #
    #                                              #
    ################################################
    #
    #

    # Specify the name of your toplevel module
    set my_toplevel  Circuit298
    set verilog_input Circuit298chains4

    ################################################
    # No changes required below
    ################################################


    #global env
    #set OSU_FREEPDK $env(OSU_FREEPDK)

    global rda_Input
    set rda_Input(ui_netlist) $verilog_input.v
    set rda_Input(ui_timingcon_file) $my_toplevel.sdc
    set rda_Input(ui_topcell) $my_toplevel

    set rda_Input(ui_netlisttype) {Verilog}
    set rda_Input(ui_ilmlist) {}
    set rda_Input(ui_settop) {1}
    set rda_Input(ui_celllib) {}
    set rda_Input(ui_iolib) {}
    set rda_Input(ui_areaiolib) {}
    set rda_Input(ui_blklib) {}
    set rda_Input(ui_kboxlib) ""
    set rda_Input(ui_timelib) "/home/akumar3/intr/benchmarks/iscas89/s298/NangateOpenCellLibrary_typical_conditional_nldm_new.lib"
    set rda_Input(ui_smodDef) {}
    set rda_Input(ui_smodData) {}
    set rda_Input(ui_dpath) {}
    set rda_Input(ui_tech_file) {}
    set rda_Input(ui_io_file) ""
    set rda_Input(ui_buf_footprint) {buf}
    set rda_Input(ui_delay_footprint) {buf}
    set rda_Input(ui_inv_footprint) {inv}
    set rda_Input(ui_leffile) "/home/akumar3/Downloads/NangateOpenCellLibrary_PDKv1_3_v2009_07/lef/NangateOpenCellLibrary1.lef"
    set rda_Input(ui_core_cntl) {aspect}
    set rda_Input(ui_aspect_ratio) {1.0}
    set rda_Input(ui_core_util) {0.7}
    set rda_Input(ui_core_height) {}
    set rda_Input(ui_core_width) {}
    set rda_Input(ui_core_to_left) {}
    set rda_Input(ui_core_to_right) {}
    set rda_Input(ui_core_to_top) {}
    set rda_Input(ui_core_to_bottom) {}
    set rda_Input(ui_max_io_height) {0}
    set rda_Input(ui_row_height) {}
    set rda_Input(ui_isHorTrackHalfPitch) {0}
    set rda_Input(ui_isVerTrackHalfPitch) {1}
    set rda_Input(ui_ioOri) {R0}
    set rda_Input(ui_isOrigCenter) {0}
    set rda_Input(ui_exc_net) {}
    set rda_Input(ui_delay_limit) {1000}
    set rda_Input(ui_net_delay) {1000.0ps}
    set rda_Input(ui_net_load) {0.5pf}
    set rda_Input(ui_in_tran_delay) {120.0ps}
    set rda_Input(ui_captbl_file) {/home/akumar3/Downloads/NangateOpenCellLibrary_PDKv1_3_v2009_07/technology/techfile/encounter/NCSU_FreePDK_45nm.capTbl}
    set rda_Input(ui_cap_scale) {1.0}
    set rda_Input(ui_xcap_scale) {1.0}
    set rda_Input(ui_res_scale) {1.0}
    set rda_Input(ui_shr_scale) {1.0}
    set rda_Input(ui_time_unit) {none}
    set rda_Input(ui_cap_unit) {}
    set rda_Input(ui_sigstormlib) {}
    set rda_Input(ui_cdb_file) {}
    set rda_Input(ui_echo_file) {}
    set rda_Input(ui_qxtech_file) {}
    set rda_Input(ui_qxlib_file) {}
    set rda_Input(ui_qxconf_file) {}
    set rda_Input(ui_pwrnet) {VDD}
    set rda_Input(ui_gndnet) {VSS}
    set rda_Input(flip_first) {1}
    set rda_Input(double_back) {1}
    set rda_Input(assign_buffer) {0}
    set rda_Input(ui_pg_connections) [list \
                            {PIN:VDD:} \
                            {PIN:VSS:} \
                                  ]
    set rda_Input(PIN:VDD:) {VDD}
    set rda_Input(PIN:VSS:) {VSS}

    --------------------------------------------------------------------------------------------------------------------------------

    Encounter Script

    ------------------------------------------------------------------------------------------------------------------------------


    # Create Initial Floorplan
    floorplan -r 1.0 0.6 40 40 40 40

    # Create Power structures
    addRing -spacing_bottom 5 -width_left 5 -width_bottom 5 -width_top 5 -spacing_top 5 -layer_bottom metal5 -width_right 5 -around core -center 1 -layer_top metal5 -spacing_right 5 -spacing_left 5 -layer_right metal6 -layer_left metal6 -nets { VSS VDD }

    clearglobalConnects
    globalNetConnect VDD -type tiehi -all
    globalNetConnect VDD -type pgpin -pin VDD -override -all

    globalNetConnect VSS -type tielo -all
    globalNetConnect VSS -type pgpin -pin VSS -override -all
    # Route power nets
    sroute -noBlockPins -noPadRings

    # Place standard cells
    placeDesign
    getNanoRouteMode -quiet
    getNanoRouteMode -quiet envSuperthreading
    getNanoRouteMode -quiet drouteFixAntenna
    getNanoRouteMode -quiet routeInsertAntennaDiode
    getNanoRouteMode -quiet routeAntennaCellName
    getNanoRouteMode -quiet timingEngine
    getNanoRouteMode -quiet routeWithTimingDriven
    getNanoRouteMode -quiet routeWithEco
    getNanoRouteMode -quiet routeWithSiDriven
    getNanoRouteMode -quiet routeTdrEffort
    getNanoRouteMode -quiet routeWithSiPostRouteFix
    getNanoRouteMode -quiet drouteAutoStop
    getNanoRouteMode -quiet routeSelectedNetOnly
    getNanoRouteMode -quiet drouteStartIteration
    getNanoRouteMode -quiet envNumberProcessor
    getNanoRouteMode -quiet envSuperthreading
    getNanoRouteMode -quiet routeTopRoutingLayer
    getNanoRouteMode -quiet routeBottomRoutingLayer
    getNanoRouteMode -quiet drouteEndIteration
    getNanoRouteMode -quiet routeEcoOnlyInLayers
    globalDetailRoute


    streamOut final_pg.gds2 -mode ALL -stripes 1 -units 10000 -mapFile gds2_encounter1.map   -merge /home/akumar3/Downloads/NangateOpenCellLibrary_PDKv1_3_v2009_07/gds/*.gds -uniquifyCellNames



    saveNetlist -phsy final.v


    # Run DRC and Connection checks
    verifyGeometry
    verifyConnectivity -type all

    win
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  • Kari
    Kari over 15 years ago

     First of all, if this is a direct cut-n-paste of your script, you have the -phys parameter of saveNetlist spelled wrong.

    But, if all you want is RCs, You can get those right from Encounter.

    setExtractRCMode -coupled true
    extractRC
    rcOut -spf myDesign.spf

    The only part I'm not sure about is the last one - I don't know if that will give you dspf or not. (Most people use SPEF these days.)

    If you want sign-off quality extraction, you should run QRC, but that may require a bit more setup.

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  • asinghct
    asinghct over 15 years ago

    Thans for your reply. Actually, I am getting spf from encounter. But the spef I am getting has all coupling capicatnes included, but spf do not have coupling capicatines. 

    I tried detailed mode , with coupling capicitances on option 

    We have to feed this to  our code --that does processing, unfortnately it reads only spf/dspf only not spef

    thanks 

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