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How to find ThroughPin(s) for generated clock

MMode

Hi all,

in our design we use a number of generated clocks, i.e. the main clock is for instance divided by 13339. The clock dividers are specified as generated_clock in the SDC file. Now, we would like to build a clock tree for the main clock including the generated clock domains. This should be possible with the ThroughPin feature of the clocktree spec. However, we are unsure of how to correctly define our scenario using ThroughPins. Do we actually need to specify a ThroughPin entry for every bit of the counter that divides the clock? Or is this the wrong approach anyway?

 

We have tried some approaches by now but still cannot achieve timing closure on our design, so we would be thankful for any suggestions and background explanations.

Parents

  • Thank you for your hints, that was very helpful - we considered the ThroughPin spec to be mandatory for every generated clock, this does not seem to be correct.

    We checked the clock trace, it shows that the registers in questions are sinks of the clock tree, so you are right, the ThroughPin does not seem to be necessary here. However, we do not reach a setup WNS better than -3 ns for the generated clock during postCTS and postRoute optimizations - even though there is enough space and the divided clock is really slow.

    Do you have any other suggestions where we might locate the problem? According to the clock trace, the clock tree does not seem to be the problem.

Reply

  • Thank you for your hints, that was very helpful - we considered the ThroughPin spec to be mandatory for every generated clock, this does not seem to be correct.

    We checked the clock trace, it shows that the registers in questions are sinks of the clock tree, so you are right, the ThroughPin does not seem to be necessary here. However, we do not reach a setup WNS better than -3 ns for the generated clock during postCTS and postRoute optimizations - even though there is enough space and the divided clock is really slow.

    Do you have any other suggestions where we might locate the problem? According to the clock trace, the clock tree does not seem to be the problem.

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