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Scan Reorder issue

Vishnu Chada

We have a scan connection as follows :

               FF1(from Q,SDFF)   -----------BUF ---------------FF2 (to D , DFF)
                                                                                 |
                                                                                 |
                                                                                 ________(to other logic)


Scan def :

+ORDERED
        FF1 ( IN SI ) ( OUT Q )
        FF2  ( IN D ) ( OUT Q )
+FLOATING
         ---
        ---

When i do scan reordering the tool mess with the functional path which is shown in above representation.Connects that entire logic to other flop, which is caught in lec.It does not honor the ORDERED section properly.Is there any known issue where encounter has problem handling Regular Flop (with D input as part of the scan chain) in the ORDERED section instead of a ScanFlop ?

Tried using 7.1 and 8.1USR3.

Appreciate your help.

Regards,
Vishnu

Parents
  • maxb

    I had similar issues with EDI 9.12. Some flip-flops with scan input D instead of SI was marked as mismatch by LEC. During scan reordering with EDI warnings were issued about removing inverters in the scan chain and then having to correct logic:

    Successfully traced scan chain "chain0_seg1_clk_rising" (1939 scan bits).
    *info: delete instance top/subdesign/g5048 (INV_X1M_A12TR) along scan chain!
    **WARN: (ENCSC-1152):    In DEF scan chain "chain0_seg1_clk_rising", " g5048 ( IN A ) ( OUT Y ) ( BITS 1 ) " is skipped because the instance can not be found.
    **WARN: (ENCSC-1135):    In scan chain "chain0_seg1_clk_rising" DEF ordered section, buffers or logics following scan instance "top/subdesign/state_reg[2]" are corrected to match the netlist.
     

    after changing setScanReorderMode -skipMode from "skipTwoPinCell" to "skipNone" the warnings went away and the equivalency check was passing. I did not analyze exactly what went wrong in the first place though.

Reply
  • maxb

    I had similar issues with EDI 9.12. Some flip-flops with scan input D instead of SI was marked as mismatch by LEC. During scan reordering with EDI warnings were issued about removing inverters in the scan chain and then having to correct logic:

    Successfully traced scan chain "chain0_seg1_clk_rising" (1939 scan bits).
    *info: delete instance top/subdesign/g5048 (INV_X1M_A12TR) along scan chain!
    **WARN: (ENCSC-1152):    In DEF scan chain "chain0_seg1_clk_rising", " g5048 ( IN A ) ( OUT Y ) ( BITS 1 ) " is skipped because the instance can not be found.
    **WARN: (ENCSC-1135):    In scan chain "chain0_seg1_clk_rising" DEF ordered section, buffers or logics following scan instance "top/subdesign/state_reg[2]" are corrected to match the netlist.
     

    after changing setScanReorderMode -skipMode from "skipTwoPinCell" to "skipNone" the warnings went away and the equivalency check was passing. I did not analyze exactly what went wrong in the first place though.

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