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Generate statement in RTL compiler version 9.1

deeps4

Hi All,

I observe that  RTL compiler 9.1  does not suppor genvar/generate for  constructs. Are there any other alternatives other than this construct that I can use.

 Thanks,

Regards,

-Deepak

 

 

 

  •  Hi Deepak,

     I wonder what message made you draw that conclusion. Those are v2001 constructs which have always been supported by RC. You either have to enable v2001 or systemVerilog to enable those constructs using

     set_attr hdl_language (v2001|sv)  /

    or

    read_hdl -(v2001|sv) <files>

    Please share what made you think they were not supported

    regards,

    gh-

     

     

     

  • It does support with -v2001 extension but is there a way not to use -v2001extension  but yet be able to instantiate multiple modules.Kind of simulate the effect of generate with some other constructs?

     

     

     

  • Hi Deepak,

    v95 does not support the generate statement. It is not part of the LRM for IEEE1364-1995. I am curious what is the fear of using v2001 or sv. They are simply supersets of v95 and should not have any impact on QoR. Only possible issues are the use of additional reserved keywords but unlikely to overlap with your signal names.

    gh-

  •  Yeah , I will go ahead use the construct. As you mentioned it doesnt overlap with my any other keywords.

    Thanks a lot for the info.

     

     

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