How to implement dual threshold voltage in a circuit?

 Can you be more specific about what you're trying to do? If you're asking "How do I work with multi-VT libraries in Encounter", then that's pretty easy. Just load in the .lib and LEF files of the different VT cells and Encounter can use them. If you do a leakage opt, for example, Encounter will know to swap out the leaky VT cells for less-leaky ones without breaking timing.

 Hi,,

 i have seen ur post. U have been posted it a year ago.. I think u might have done the thing using dual threshold vge technique.. Am doing project in the same topic. I ll send my base paper along with this msg. pls go thro it and give me idea asap. Am having cadence tool with me. 

Effectiveness Analysis ofLow Power Technique of
Dynamic Logic under Temperature and Process
Variations
Jinhui Wang*, Wuchen Wu, Na Gong, Wang Zhang, and Ligang Hou
Abstract - Using multiple-parameter Monte Carlo method,
the effectiveness ofthe dual threshold voltage technique (DTV)
in low power domino logic design is analyzed. Simulation
results indicate that under significant temperature and
process variations, DTV is still highly effective to reduce the
total leakage and active power consumption for domino gates
with speed loss. Also, regarding power and delay
characteristics, different structure domino gates with DTV
have different robustness against the temperature and process
variation',
Index Terms - domino gate, temperature and process
variation, effectiveness.
I. INTRODUCTION
Dynamic circuits, in particular domino gates are often
applied in high speed digital circuits due to their fast
evaluation and small area merits [1]-[3]. However, as
technology scales down, the leakage power of domino logic
increases exponentially with the scaling of the threshold
voltage (Vt) and gate oxide thickness (tax} By the sub-65nm
generation, leakage power may constitute as much as 50
percent of the total power consumption [4], [5].
The dual threshold voltage technique (DTV) [6] is one of
most popular techniques to suppress leakage power. However,
as the technology scales down below 65 nm node, the
increasing die-to-die and with-in chip variations bring a great
challenge to low power techniques, including DTV. Two main
contributors to variations are changes in process parameters
and changes in operating temperatures. Also, the exponential
relation between leakage current and temperature makes the
effect of process variations vary at different temperature.
Therefore, there exists the need to investigate the
effectiveness of DTV under process and temperature
variations to help designers judge if the DTV application in
circuits could meet the frequency-leakage requirements in
sub-65 nm era. Many researchers have utilized Monte Carlo
method to analyze the effectiveness of DVT with variations,
but they still could not solve the problem completely. Some of
them only focus on one variation and ignore the relations of
two variations [7]. Others analyze process variations only
This work was supported in part by the PhD Student Innovation Program
of Beijing University of Technology under Grant No. bcx-2009-015.
Jinhui Wang, Wuchen Wu, Ligang Hou, and Wang Zhang are with VLSI
& System Lab, Beijing University of Technology, Beijing 100022, China
(Tel:+86-1067391638 e-mail: wangjinhui888@ yahoo.com.cn).
Na Gong is with College of Electronic and Info Engineering, Hebei
University, Baoding, 071002, China (e-mail: nagong_china@yahoo.com).
978-1-4244-3870-9/09/$25.00 ©2009 IEEE
1236
under worse case temperature and fail to consider the uniform
change of temperature in practice [4], [8]. In this paper,
utilizing multiple-parameter Monte Carlo method, the
effectiveness of DTV in low power domino logic is analyzed
at the presence of simultaneous variations of process and
temperature.
II. DYNAMIC CIRCUITS WITH DTV
DTV could suppress the leakage power efficiently and
therefore it has been applied widely in VLSI design [6]. As
can be seen from Fig.l, taking the domino OR gates with
DTV as an example, the critical signal transitions determining
the domino circuit delay occur along the evaluation path. In a
dual V, domino circuit, therefore, all of the transistors,
activated during the evaluation phase (Nclk, Nl ......Nn, Pr),
have a low V, Alternatively, the precharge/predischarge phase
transitions (PI, P2, Nr) are not critical for the performance of
a domino circuit and they are high V, transistors [9]. It is
operated as follows. In the precharge phase, the clock is set
low. PI is turned on. And the evaluation phase begins when
the clock is set high. PI is cut off. Provided that the necessary
input combination to discharge the evaluation node is applied,
the circuit evaluates and the dynamic node is discharged to
ground. Otherwise, the high state of the dynamic node will be
preserved until the following precharge phase [10].
In the idle stage, the leakage power of domino circuits is
produced by leakage current which is dominated by the subthreshold
leakage current, which can be expressed by equation
(1) [11]. In the active stage, the active power of domino
circuits also contains two parts: the dynamic switching power
and the leakage power.
I = Weff
q£SiNch V2 {VgS
- ~ J(l- (- Vds JJ (1) sub Ueff T ex exp
L~ 2$s n~ ~
where ueffi Weffi Leffi e sis Nch, C/Js» and VT are effective carrier
mobility, effective channel width, effective channel length,
thermal voltage, permittivity of silicon, effective channel
doping, surface potential and sub-threshold swing,
respectively. From (1), it can be seen that the sub-threshold
leakage current decreases exponentially with the increasing of
V, Thus, DTV can lower both the leakage and active power.
III. TEMPERATURE AND PROCESS VARIATIONS
Process variations occur due to proximity effects in
photolithography, non-uniform conditions during deposition,
random dopant fluctuation, etc. [12]. These cause fluctuations
in parameters such as channel length, width, oxide thickness,
Vdd
Vdd
Gn
Vdd
r---~r=rC---l
: I
: Low Vt device : i 4[~I[ l I PU,1<~ll"l Input_~I"'I'" , \
I
I H. h II ~ - Nl - Nn ,.
output l 19 Vt device: \,v-~; 1J -J -_
II Nr i "---""\ :---II N~ik--------d~~amiC
: ',...__-,' : c lock node
: Pull-down :
I I
: ~~_t!.~:r.:~ ]
(a) (b)
Fig.l Domino OR gates (a) domino gate with Low Vt (b) domino gate with dual Vt
Gn
IV. MONTE CARLO ANALYSIS
In this section, a quantitative analysis is provided to
investigate the effectiveness of DTV in suppressing the power
consumption of domino gates under temperature and process
fluctuations. Domino circuits with different structures of the
pull-down networks (PDN), such as 2-input, 4-input, 8-input,
and 16-input domino OR gate (OR2, OR4, OR8, and OR16,
respectively), 2-input and 8-input domino AND gates (AND2
and AND8), 2-bit and 16-bit domino multiplexer (MUX2 and
Vt (T) = Vt (To)+(KT1 + KT1L + VbSefJKT2J X (~-lJ (4)
i; To
PMOS:
~(T) =Vt(To)-(KT1+ KT1L + VbsefJKT2JX(~-lJ(5)
LefJ To
u.g(T) = [u{kf]- (6)
{I + (Vg""ff 7:).:~(T))' Ub(T) + (uJr)vb"ff +Uam{ Vg"'ff7:x:~(T))} ~1
where KT1, KTlL, KT2, Vbsejfi u; Ute, TOXE, u; u; o; To,
and T are the temperature coefficient for threshold voltage,
channel length dependence of the temperature coefficient for
threshold voltage, body-bias coefficient of threshold voltage
temperature effect, effective substrate bias voltage, mobility at
the reference temperature, mobility temperature exponent,
electrical gate-oxide thickness, first order mobility
degradation coefficient, second order mobility degradation
coefficient, body effect of mobility degradation coefficient,
reference temperature, and the operating temperature,
respectively. KT1, KT1L, and KT2, are constant empirical
parameters while Ua, Ub, and Ui; are temperature dependent.
(1), (4), (5), and (6) indicate that temperature fluctuation lead
the variation ofVt which determines the delay and the leakage
of the circuits.
45nm
O.22V O.35V
-O.22V -O.35V
O.8V O.8V
TABLE I
PARAMETER OF DEVICES
Technology Node
NMOS threshold voltage
PMOS threshold voltage
Supply voltage
as well as dopant concentrations, and result in variations in V,
which determines the delay and the leakage of the circuits.
Among the variations in transistor parameters, variations in
gate length and threshold voltage are found to have the most
significant impacts on circuit performance and power
consumption [7]. The standard deviation of the intrinsic
threshold voltage for long channel devices is analytically
modeled as:
(J"~ =(!LJ NchWDEP (2)
tox 3WL
where q is the charge, tox is the gate oxide capacitance, Nch is
the weighted doping concentration, WDEP is the channel
depletion width, and Wand L are the channel width and gate
length, respectively. This equation is derived for long channel
devices which do not exhibit short channel effects. As shown
in equation (2), the variation in threshold is caused by the
doping un-uniformity and is proportional to the square root of
doping concentration and inversely proportional to the square
root of device gate length and channel width.
In nanometer technologies, the shorter device gate length
reduces the effective threshold voltage to
~h = ~hO - f1~h (~h _roll_ off)- f1~h(DIBL) (3)
where Voo is the intrinsic threshold voltage, L1
Vth(Vth _roll_off) and L1 Vth(DIBL) are the drop in threshold
voltage due to short channel effect and DIBL, respectively.
The relation between the gate length and threshold roll-off and
DIBL is exponential and thus when there are variations in gate
length, the net effect is increased variation in threshold
voltage.
Changes in the operating temperature occur due to power
dissipation in the form of heat. On-chip thermal variations
have a significant bearing on the mobility of electrons and
holes, as well as the threshold voltage of the devices. An
increase in the operating temperature causes the mobility to
decrease, thereby decreasing the on-current, which, in turn,
can reduce the speed of the circuit. Further, elevated
temperatures also lead to an increase in the leakage current
[13]. The impact of temperature fluctuations on the leakage
current and V t in a MOSFET is identified utilizing BSIM4
MOSFET equations. v, and ueffofa MOSFET are [14]
NMOS:
1237
t 0.5
ox (7)
where v is the speed of the transistor, and other parameters
have their usual meanings. (7) shows that v decreases greatly
as Vt increases,
is lower than 388nW. Alternatively, 70% of the samples with
the low V, transistors consume leakage power higher than
388nW. These results indicate that DTV is highly effective to
reduce the total leakage power consumption even under
significant process and temperature variations. Also, two
active power distribution curves intersect at 15uW. The active
power consumption of 91% of the dual V, samples is lower
than 15uW and 90% of the low V, samples consume active
power higher than 15uW. This is because the active power
consists of the switching power and the leakage power and
DTV can be effective to suppress leakage power, thereby
reducing the total active power.
As also can be seen from Fig. 2, the delay of all 4-input OR
sample gates (100%) with DTV is lower than 490pS, while
that of all low V, samples (100%) is higher than 490pS.
Obviously, under the effect of the temperature and process
variations, the inferior speed characteristics of the high V,
transistors in circuit with DTV still induce the speed penalty
as expressed in equation (7) [9]
( J
1.3
V 0.3 1-~
dd V
dd vex:--------
MUX16), are employed as the benchmark circuits. They are
simulated based on 45nm BSIM4 models [15] by the HSPICE
tool. Each domino gate drives a capacitive load of 8fF. The
parameters of devices are listed in table I. All gates are turned
to operate at 1GHZ clock frequency and W/L in PDN is set to
5-20 [16]. When simulating the leakage power, all of the
domino OR gates are set in CHIH (clock=l, In_1= In_2= ...
In_n =1) state, which can ensure every gates in the lowest
leakage state [6].
To evaluate the impact of process and temperature
variations on the effectiveness of DTV, process and
temperature variations aware power and speed characteristics
of domino circuits with DTV is evaluated using multipleparameter
Monte Carlo analysis. In our simulation, three most
important process parameters to influence the performance of
the MOSFET are considered: gate length (Lgate) , channel
doping concentration (Nch) , and gate oxide thickness (tox) . And
these parameters are all assumed to have normal Gaussian
statistical distributions with a three sigma (30) variation of
10%. In addition, temperature is assumed to have uniform
distribution and varies the normal value (75°C) by ± 50°C.
1000 Monte Carlo simulations are run to evaluate the power
and delay distribution of different domino gates.
Taking 4-input dual V, OR gate as an example, its leakage
power, active power and delay characteristics at the presence
of process and temperature variations are shown in Fig. 2. As
can be seen from it, the leakage power distribution curves of
the low V, and dual V, domino OR gates cross at 388nW.
Leakage power consumption of88% of the samples with DTV
250
490pS +Dual Vt Delay
200 LowVtDelay
20
en
-(la) 00 150
§ en 80
4-.
0 100
;.... 60
(l)
..D
E
;:$ 50 Z
Leakage Power (nW)
Fig. 2 Leakage power, active power and delay distribution of 4-input dual V, domino OR gate
100
100
100
100
100
100
100
100
D<Cross/%
279 13 480 93 77 100 72 70
388 15 490 88 91 100 70 90
611 16 530 86 74 100 70 66
938 19 540 65 66 100 60 79
705 19 591 82 87 100 61 64
2021 20 676 69 61 100 52 90
388 22 460 88 86 100 70 95
1650 23 632 63 96 100 61 94
OR2
OR4
OR8
OR16
AND2
AND8
MUX2
MUX16
TABLE II
DISTRIBUTION OF LEAKAGE POWER, ACTIVE POWER AND DELAV OF THE DOMINO GATES (L: LEAKAGE POWER; A: ACTIVE POWER; D: DELAv)
Gate Cross Dual Vt Low Vt
L/nW A/uW DipS L<Cross/% A<Cross/% D>Cross/% L>Cross/% A>Cross/%
1238
D(pS)
TABLE III
THE AVERAGE AND STANDARD DEVIATIONS (SD) OF THE DOMINO GATES (L: LEAKAGE POWER; A: ACTIVE POWER; D: DELAY)
Gate Dual Vt Low Vt
(Average/SD) L(nW) A(uW) D(pS) L(nW) A(uW)
OR2 195/72.0=2.70 13/0.94=13.83 589/34.8=16.91 590/371=1.58 15.4/1.1=14.00
OR4 286/115=2.49 13.1/0.9=14.89 598/35.4=16.91 682/394=1.73 16.2/1.1=15.12
OR8 467/200=2.33 15.0/1.0=15.03 656/45.6=15.07 865/450=1.92 17.2/1.1=15.54
OR16 913/411=2.22 18.7/1.2=16.22 489/32.7=17.97 1338/625=2.14 21.0/1.2=18.23
AND2 583/253=2.30 18.1/1.00=18.1 683/29.5=23.19 984/491=2.01 20.2/1.84=10.99
AND8 1939/868=2.23 19.6/2.00=9.79 787/25.8=30.47 2398/1089=2.20 23.5/2.62=8.98
MUX2 285/114=2.49 21.9/0.89=24.5 532/28.8=18.45 685/398=1.72 24.4/1.01=23.10
MUX16 1711/754=2.27 21.5/0.87=24.61 544/36.8=14.78 2.64/934=2.21 24.8/1.11=22.28
425/15.2=28.00
417/15.1=27.64
446/12.2=36.68
315/12.2=25.85
450/11.0=40.90
584/15.6=37.27
409/16.10=25.37
362/12.75=28.43
Table II lists the leakage power, active power and delay
characteristics of OR2, OR4, OR8, OR16, AND2, AND8,
MUX2, and MUX16 domino gates. As indicated in it, with the
increasing number of the inputs, the values of the point of
intersection of the leakage power, active power and delay all
increase gradually. As to leakage power and active power,
over 50% samples of all of the dual V, domino gates are
smaller than the cross, and alternatively over 50% samples of
all of the low V, domino gates are lager than the cross.
Therefore, under the effect of the temperature and process
variations, DTV is still quite effective to reduce the total
leakage and active power consumption for all style of domino
gates with speed loss.
The average and standard deviations (SD) of dual V, and
low V, domino gates are listed in Table III. The Average/SD
values of the leakage power of all the dual V, gates are larger
than that of the low V, gates, which shows that DTV can
sustain the availability of suppressing leakage power with the
process and temperature variation.
Also can be seen form Table III, the Average/SD value of
delay of all domino gates with DTV are less than that of the
low V, gates and therefore DTV could weaken the immunity
of the domino gates to process and temperature variation
regarding the delay characteristics.
In addition, as to domino OR gates with DTV, the
Average/SD value of active power are less than that ofthe low
Vt OR gates, but the Average/SD value of active power of
AND and MUX gates with DTV are larger than that of the
low V, gates. This is because in the PDN of AND and MUX
gates, the transistors are cascaded and thereby produce stack
effect to lower the leakage power, which improve the
robustness of domino gates against effect of process and
temperature variation.
v. CONCLUSION
Effectiveness of the dual threshold voltage technique (DTV)
in domino logic design is analyzed based on multipleparameter
Monte Carlo simulation. Simulation results indicate
that DTV is highly effective to reduce the total leakage and
active power consumption for domino gates with speed loss
under significant temperature and process variations. And
DTV can sustain the availability of suppressing leakage power
in domino gates with different structures. However, DTV
could weaken the immunity of the domino gates to process
and temperature variation regarding the delay characteristics.
As to the active power, the domino AND and MUX gates with
DTV have more robustness against process and temperature
variation than domino OR gates.
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