Finding common clock path in the design

Before doing timing analysis, using

setAnalysisMode -cppr both

removes pessimism from clock paths that have a portion of the
clock network in common between the clock source and clock
destination paths.
The pessimism is introduced when the timing analysis tools
assume that the common path has different delay values for two
different paths in case of on-chip variation. The pessimism can
also be because of clock reconvergence in the clock network.
The pessimism effects all analysis modes including single, best
case-worst case (bcwc), and on-chip variation.
For more information, see “Removing Common Path
Pessimism”, in the Encounter User Guide.