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Nanoroute seems not to connect IO Pad pins to nets

kasyab

The problem I have is stated in the subject. I tracked this through a number of warnings at differnet phases in the flow.

1) The first trial route during  pre-cts optimization issues the following warning:

 **WARN: (ENCTR-2325):    42 nets connect a pad term to a fterm without geometry and will not be routed.

This however,does not stop the optimization engine and the flow continues. Trial route completes giving an accurate picture of how things should be.

 2) When nanoroute is invoked a whole bunch of these warnings are issued:

 #WARNING (NRDB-733) PIN AHB_ADDR_PAD[22] in CELL_VIEW CHIP,init does not have physical port
#WARNING (NRDB-733) PIN AHB_ADDR_PAD[23] in CELL_VIEW CHIP,init does not have physical port
#WARNING (NRDB-733) PIN AHB_ADDR_PAD[24] in CELL_VIEW CHIP,init does not have physical port
#WARNING (NRDB-733) PIN AHB_ADDR_PAD[25] in CELL_VIEW CHIP,init does not have physical port
#WARNING (NRDB-733) PIN AHB_ADDR_PAD[26] in CELL_VIEW CHIP,init does not have physical port
#WARNING (NRDB-733 Repeated 20 times. Will be suppressed.) PIN AHB_ADDR_PAD[27] in CELL_VIEW CHIP,init does not have physical port
#WARNING (EMS-27) Message (NRDB-733) has exceeded the current message display limit of 20

I found an earlier post here just now explaining what this warning means. In light of the previous warning, I think these re related but still no closer to a solution.

This issue passed the geometry and connectivity checks in EDI (run with default options) and came to light when I ran DRC with Calibre.

Any help is appreciated.

Thanks

Kasyab 

PS: I have pictures  of the connectivity at the pad pins after TrialRoute and NanoRoute, but am not sure how to upload them.

Parents

  • Hi Bob,

       Thank you for your quick response. I have confirmed that all the IO macro's  are marked CLASS PAD INOUT. However, I think in this case the warnings I flagged must be erroneous, because the DRC errors flagged at the pads are related to min width and  slotting. With virtually no experience with signoff (have mainly dealt with RTL stuff and verification in the past, but this is the first time I am handling a design till signoff) I could be wrong and if so, please correct me.

    All the same I think it is interesting to know when, these warnings can be ignored and why the visualization is the way it is.

     

    Kasyab

Reply

  • Hi Bob,

       Thank you for your quick response. I have confirmed that all the IO macro's  are marked CLASS PAD INOUT. However, I think in this case the warnings I flagged must be erroneous, because the DRC errors flagged at the pads are related to min width and  slotting. With virtually no experience with signoff (have mainly dealt with RTL stuff and verification in the past, but this is the first time I am handling a design till signoff) I could be wrong and if so, please correct me.

    All the same I think it is interesting to know when, these warnings can be ignored and why the visualization is the way it is.

     

    Kasyab

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