Macromodel Definition for blocks at Top Level

Hi,

I'm tyring to validate whether the CTS step has considered the macromodel definitions I defined in the clock spec file for the blocks during my CTS at the Top Level i.e. Full Chip Level.

I have the following macro model defined on a particular block. block_abc is the module/cell name of the block and clk  is the pin on which I defined the macromodel.
#MacroModel pin <pin> <maxRiseDelay> <minRiseDelay> <maxFallDelay> <minFallDelay> <inputCap>
MacroModel port block_abc/clk 453.3ps 285.1ps 478.8ps 307.6ps 0fF hold_func level 15 8
MacroModel port block_abc/clk 981.5ps 776.1ps 1052ps 766.1ps 0fF setup_func level 15 8


In the clock.report which the encounter dumps after the CTS step, I see the following behavior:
Min trig. edge delay at sink(R): block_abc_inst/clk 4750.4(ps) *Mmodel*

However, when I try to get the latencies for all the block clock pins at the Top Level, the block_abc_inst/clk has the f
ollowing latency.

report_clock_timing -to block_abc_inst/clk -type latency
        ---Latency---
    Source        Network          Total         Clock Pin
---------------------------------------------------------------------------
      0.000         3.166          3.166        f    block_abc_inst/clk

So, I'm just wondering whether the tool is including the macromodel defn (i.e. the delay associated) when i execute the above command?

The main reason for the question arised due to the fact that I'm seeing approximately the same latency at the clock pins for all the blocks in the Top Level, inspite of these blocks having different delay values in their respective macromodel definitions. All these blocks are driven by the same clock.

Thanks,

gsc104