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Extracted Timing Models ETS 8.1

NigH

I have created a WC timing model for my design and in the validation process for ETM(Extracted Timing Model), it has shown failures in the compare report.

The arrival times for some output ports show up to 40% of a difference between the spef flow and after the ETM is read in.

Can anyone suggest possible reasons for this?

  Already I have checked if the constraints have caused the problem but I think thats ruled out as the root of the problem.

command used: 

do_extract_model  results/f1_test.wc.lib -blackbox -verilog_shell_file results/f1_test.wc.v

 

Many thanks

Nigel 

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