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EDI sdc read in error.

coffeelox

I am using EDI 9.1.

In verilog file, I defined PI_CLKI as port for clki in

PIC U_PI_CLKI ( .P(PI_CLKI), .IE(VDD), .Y(clki));

In sdc file, I put the following statement...

create_clock -name "PI_CLKI"  -period 410  -waveform {0 205} [get_ports {PI_CLKI}]

In Encounter, set rda_Input(ui_timingcon_file) to the sdc file defined above in conf file. While load the conf file, I got the following errors... anybody can help? I really have no clue....

CTE reading timing constraint file '/amd/homes/d/jsun4/c130nm_v1.6/ni1_v1.7/digital/synopsys_work_dir/Synthesized/sar_adc_8bits_i2c_top.201010122_v1_wPad.sdc' ...
**WARN: (TCLCMD-513):    No matching object found for 'PI_CLKI' (File /amd/homes/d/jsun4/c130nm_v1.6/ni1_v1.7/digital/synopsys_work_dir/Synthesized/sar_adc_8bits_i2c_top.201010122_v1_wPad.sdc, Line 24).

**ERROR: (TCLCMD-917):    Cannot find 'ports' that match 'PI_CLKI' (File /amd/homes/d/jsun4/c130nm_v1.6/ni1_v1.7/digital/synopsys_work_dir/Synthesized/sar_adc_8bits_i2c_top.201010122_v1_wPad.sdc, Line 24).

**ERROR: (TCLCMD-1109):    Could not find source for create_clock command (File /amd/homes/d/jsun4/c130nm_v1.6/ni1_v1.7/digital/synopsys_work_dir/Synthesized/sar_adc_8bits_i2c_top.201010122_v1_wPad.sdc, Line 24).

  • coffeelox

    problem fixed... forgot to add verilog head file... :( 

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