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How to report list of flops whose clock port is driven by test clock in test mode

diablo

 Hi all,

  I have functional and test analysis views. The Test clock is muxed with functional clock whose selector is TEST_EN net.

  In my functional SDC, I have "set_case_analysis 0 TEST_EN" and in test SDC, I have "set_case_analysis 1 TEST_EN". I want to verify  whether in test analysis view, the Test clock is seen by all the flops. 

  How to report the list of flops whose clock port is driven by test clock in test analysis view.

 Thanks for your time.

  

 

Parents
  • BobD

    What an awesome question this is - thanks for posting it.

    Brian's note about the -view option on check_timing is applicable to get_property as well, which you could use to check which clocks are associated with each clock pin per view.  I created a tiny circuit to test this, with clka and clkb being muxed differently in view "a" and view "b".  You can query the clocks like this:

    encounter 11> get_property -view a [get_pins i1/CK] clocks
    clka
    0x14

    encounter 12> get_property -view b [get_pins i1/CK] clocks
    clkb
    0x16

    To loop through all of the registers in the design and check you could do something like this:

    foreach_in_collection register [all_registers] {
      foreach_in_collection pin [filter_collection [get_pins [get_property $register hierarchical_name]/*] {is_clock == true}] {
        set clk [get_property [get_property -view b $pin clocks] hierarchical_name]
        if {$clk == "clkb"} {
          Puts "Pin: [get_property $pin hierarchical_name] in view \"b\" is driven by \"clkb\""
        }
      }
    }

    Pin: i1/CK in view "b" is driven by "clkb"
    Pin: i2/CK in view "b" is driven by "clkb"

    Hope this helps!
    -Bob

Reply
  • BobD

    What an awesome question this is - thanks for posting it.

    Brian's note about the -view option on check_timing is applicable to get_property as well, which you could use to check which clocks are associated with each clock pin per view.  I created a tiny circuit to test this, with clka and clkb being muxed differently in view "a" and view "b".  You can query the clocks like this:

    encounter 11> get_property -view a [get_pins i1/CK] clocks
    clka
    0x14

    encounter 12> get_property -view b [get_pins i1/CK] clocks
    clkb
    0x16

    To loop through all of the registers in the design and check you could do something like this:

    foreach_in_collection register [all_registers] {
      foreach_in_collection pin [filter_collection [get_pins [get_property $register hierarchical_name]/*] {is_clock == true}] {
        set clk [get_property [get_property -view b $pin clocks] hierarchical_name]
        if {$clk == "clkb"} {
          Puts "Pin: [get_property $pin hierarchical_name] in view \"b\" is driven by \"clkb\""
        }
      }
    }

    Pin: i1/CK in view "b" is driven by "clkb"
    Pin: i2/CK in view "b" is driven by "clkb"

    Hope this helps!
    -Bob

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